Response Compaction Research Articles

X-Masking for Deterministic In-System Tests

Deterministic in-system tests begin to play an essential role in safety-critical applications, in large data centers, or in monitoring silicon aging, to name just a few. All of these ecosystems require periodic, high-quality tests to assure required test coverage and short test application, especially in designs that must test themselves during system operations. In order for deterministic tests to be in-system applicable, they should compact multi-million-bit test responses with unknown (X) values to small signatures. This, in turn, allows for a much faster input-only streaming and a simultaneous reduction of the on-chip-stored test data volume, a system memory, and test time. Typically, the unknown states, whose sources vary from uninitialized memories to unpredictable last-minute timing violations, render signatures unusable. Hence, test response compaction requires some form of protection. This paper presents a user-tunable X-masking scheme. It works synergistically with on-chip test compression logic by employing encoded test data to completely filter out unknown values that otherwise might reach a test response compactor such as a MISR or test result sticky-bits used by the on-chip compare framework. It makes the proposed scheme a very versatile of its kind. Experimental results obtained for several industrial cores show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on various test-related statistics.

Co-relation scan attack analysis (COSAA) on AES: A comprehensive approach

Scan based DfT is indispensable for IC testing in the semiconductor chip industry to ensure correctness of chip, both functionally and structurally. Since a higher degree of fault coverage is essential, cryptographic ICs rely on it as a standard technique during manufacturing test. Yet an invaluable tradeoff needs to be met between security and testability, because it is the observability and controllability of the sequential memory elements in the scan chain which are enhanced to facilitate testing. Well designed differential scan attacks which make use of this feature can prove to be critically pervasive to leak secret keys embedded in cryptochips. Use of response compactors ensure test cost reduction. Existing differential scan attacks target Hamming weight pairs that are unique. The motivation of our work lies in the fact that carefully fabricating additional bits in order to transform a unique Hamming weight to a non-unique one, existing attacks can be defended. In this paper, we propose Co-relation scan attack (COSAA) on AES crypto-system which can work even in the presence of test response compaction. We show our attack technique to be lethal against any possible Hamming weight model which means that the designer needs to prevent the circuit under test from a relatively broader attack surface. Our experiments show the proposed attack can successfully recover the secret key of AES with XOR compaction in 24 milliseconds using an average desktop machine.

Statistical security analysis of AES with X‐tolerant response compactor against all types of test infrastructure attacks with/without novel unified countermeasure

Advanced encryption standard (AES) crypto-algorithm design can be implemented in software and hardware. No known attacks are available that can break the AES with brute force or cryptanalysis in finite time. However, when the AES is implemented in hardware, test infrastructure such as scan chain, stimuli decompressor, response compactor and built-in self-test (BIST) are included in the normal design for making the crypto-chip easily testable after manufacturing. This test infrastructure is highly susceptible to attacks. The attacker may misuse the scan-chain content for the retrieval of secret key from AES hardware. In this study, the authors investigated scan-chain attack based on different distributions of key-related flip-flops of AES hardware implementation with X-tolerant response compactor-based test infrastructure. The modular exponentiation security scheme as a counter measure against test infrastructure attacks is proposed. In this study, the statistical security analyses are performed with and without the proposed countermeasure in case of AES hardware followed by X-tolerant test response compactor. The experimental result shows that the proposed countermeasure thwarts the attack with almost constant rate for different distributions of key-related flops in the scan-chain, and hence it is not dependent on the nature of scan-chain architecture design.

Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array

An in-array build-in self-test (BIST) scheme is proposed for the embedded resistive random access memory (RRAM) array. The BIST circuit consists of the linear-feedback-shift-register (LFSR)- based pattern generator and the multi-input signature register (MISR)-based response compactor, and both the n-stage LFSR and MISR are implemented by n + 2 in-array RRAM cells. The proposed LFSR/MISR circuit has better performance than the IMPLY-based counterpart, due to the application of the proposed three-cycle XOR gate and two-cycle shift gate with the in-array RRAM cells. And it is more area efficient comparing with the memristor ratioed logic (MRL)-based counterpart. The proposed n-stage LFSR/MISR circuit is tested by the scan chain method. The test method only has the linear time complexity. For the best of our knowledge, it is the first attempt to design the in-array BIST circuit for the RRAM array.

Genetic algorithm as self-test path and circular self-test path design method

The paper presents the use of Genetic Algorithm to search for non-linear Autonomous Test Structures (ATS) in Built-In Testing approach. Such structures can include essentially STP and CSTP and their modifications. Non-linear structures are more difficult to analyze than the widely used structures such as independent Test Pattern Generator and the Test Response Compactor realized by Linear Feedback Shift Registers. To reduce time-consuming test simulation of sequential circuit, it was used an approach based on the stochastic model of pseudo-random testing. The use of stochastic model significantly affects the time effectiveness of the search for evolutionary autonomous structures. In test simulation procedure, the block of sequential circuit memory is not disconnected. This approach does not require a special selection of memory registers such as BILBOs. A series of studies to test circuits set ISCAS’89 are made. The results of the study are very promising.

Exploiting distribution of unknown values in test responses to optimize test output compactors

Test output compactors can effectively reduce the data volume of test responses without scarifying fault coverage. However, when there are unknown values (X-bits) in the test output, the fault coverage can be severely comprised. Many compaction schemes that can handle X-bits have been developed. However, existing test response compaction schemes are designed without considering the locations of errors and X-bits. This design methodology essentially assumes that observable errors as well as X-bits are randomly distributed among all scan cells. Recent studies show that X-bits may not be randomly distributed; some scan cells could capture much more X-bits than others. In this paper, we propose to exploit the nonuniform distribution of X-bits to optimize test response compactors such that a higher compression rate is achieved with lower hardware overhead. The proposed design method is applicable to various test output compaction schemes that can handle X-bits in the test responses, including X-blocking, X-masking, and X-tolerant circuits. Experimental results show that, in the presence of X-bits, the compression results will be significantly improved with the help of the proposed method.

New Digital Testing of Analogue Circuits

This paper presents a new parametric fault detection approach for analogue circuits based on the digital signature analysis. This approach has two main parts, an analogue test pattern generator (ATPG), and an analogue test response compactor (ATRC). The proper ATPG is designed to sweep the applying sinusoidal frequencies to match the frequency domain of the analogue circuit under test (ACUT). The output test response of the ACUT is acquired via the analogue-to-digital converter (ADC). The ATRC accumulates digital samples of the output response from the ADC to generate a digital signature that can characterize the situation of the ACUT. The signature comparison is achieved based on signature boundaries and the worst-case analysis. In addition, the signature curve for each component variations inthe ACUT is presented. It combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the band-width and the passband transmission. In this paper, the hardware implementation is achieved using the field programmable gate array (FPGA) technology as the digital part and the analogue part that includes the data conversion. The digital test controller is designed to enable the proper control and synchronization of the analogue test cycle for stable digital signature generation. The presented testing approach is applied to the ACUT in the range of biomedical applications to validate it. Based on the presented hardware implementation, the signature curve for each component of the ACUT is derived for the ACUT judgment.

Parametric Fault Detection of Analogue Circuits

This paper presents a new testing approach for analogue circuits based on the digital signature analysis. In this paper, the efficient parametric fault detection approach for analogue circuits using the simulation environment is presented. This approach has three main parts, an analogue test pattern generator (ATPG), an analogue test response compactor (ATRC), and an analogue circuit under test (ACUT) model, build in the PSpice circuit simulator. The proper ATPG is designed to sweep the applying sinusoidal frequencies to match the frequency domain of the ACUT. The output test response of the ACUT is acquired via the analogue-to-digital converter (ADC). The ATRC accumulates digital samples of the output response from the ADC to generate a digital signature that can characterize the situation of the ACUT. The signature comparison is achieved based on signature boundaries based on the worst-case analysis. In addition, the signature curve for each component variations of the ACUT is presented to be illustrated as image of some parameters affected in the transfer function of the ACUT. It combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the band-with and the passband transmission. Using the signature curve, a parametric fault of each component of the ACUT can be detected under the sweep sinusoidal frequency of the ATPG. The presented testing approach is applied to the analogue benchmark circuit to validate the presented testing approach. General Terms Modeling of analogue circuit testing.

Unknown Output Values of Faulty Circuits and Output Response Compaction

When using output response compaction it is necessary to address the fact that circuits may produce unknown output values. Methods to address this issue ensure that the output response compactor would produce a unique fault-free signature that can be used for fault detection. This paper considers the unknown output values that are produced by faulty circuits. If a faulty circuit produces an unknown value when the output value of the fault-free circuit is known, the unknown faulty output value may affect the computation of a signature. The faulty signature may not be unique, and it may not always be different from a fault-free signature. The ability to verify that the fault will be detected based on its signature is thus lost. Without limiting the discussion to a particular output response compactor, the paper studies the prevalence of such faults in benchmark circuits, the prevalence of unknown faulty output values for which the corresponding fault-free values are known, and the effects of addressing this issue.

Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits

Test response compaction offers test time and data volume reduction on the output side. An on-chip circuitry, denoted as the response compactor, is utilized, compressing the responses of the circuit, and thus enabling the storage of compacted responses on the tester memory. While the test cost is thus reduced, such a circuitry may result in error masking, and hence the degradation of the fault/error coverage level. Response bits that are unknown during simulation time pose additional challenges on the design of a response compactor, as they contribute to error masking also. Assumptions regarding a particular fault model and/or distribution of unknown response bits ease the design of a response compactor; however, the coverage loss of unmodeled faults is inevitable in the presence of such a compactor. Furthermore, modeled faults also may become unobserved if the distribution of unknown bits deviates from the assumed one. In this paper, we propose a response compaction technique that is independent of any fault model. We design the response compactor based on the expected responses of the circuit under test. As a result, any originally detectable unmodeled defect or modeled fault is still detectable with the proposed compactor, regardless of the number and the distribution of the unknown response bits. The output bit-width of the proposed response compactor is also the minimum that can be achieved when original defect and fault coverage levels are delivered. We also present an analysis that can be utilized for a quick computation of parameters, such as the lower and upper bounds and the expected value for the optimal output bandwidth, which the proposed compaction methodology is capable of attaining. As the proposed technique is a test set-dependent approach, it is more suitable for application in the domain of core-based system-on-chips (SOCs), wherein a set of test vectors and expected responses is delivered along with a core. Parallelism among core tests is increased by narrowing down the bit-width for each core, delivering test time reduction for the SOCs.

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame circuit model can specify many more inputs. A new scan architecture is proposed to compress test stimulus data, compact test responses, and reduce test application time for LOC delay fault testing. The new scan architecture merges a number of scan flip-flops into the same group, where all scan flip-flops in the same group are assigned the same values for all test pairs. Sufficient conditions are presented for including any pair of scan flip-flops into the same group for LOC transition, non-robust path delay, and robust path delay fault testing. Test data for LOC delay testing based on the new scan architecture can be compressed significantly. Test application time can also be reduced greatly. Sufficient conditions are presented to construct a test response compactor for LOC transition, non-robust, and robust path delay fault testing. Folded scan forest and test response compactor are constructed for further test data compression. Sufficient experimental results are presented to show the effectiveness of the method.

Multi-modal response compaction adaptive to x-density variation

Scan architectures with compression support have remedied the test time and data volume problems of today's sizable designs. On-chip compression of responses enables the transmission of a reduced volume signature information to the ATE, delivering test data volume savings, while it engenders the challenge of retaining test quality. In particular, unknown bits (x's) in responses corrupt other response bits upon being compacted altogether, masking their observation, and hence preventing the manifestation of the fault effects they possess. In this work, we propose the design and utilisation of a response compactor that can adapt to the varying density of x's in responses. In the proposed design, fan-out of scan chains to XOR trees within the compactor can be adjusted per pattern/slice so as to minimise the corruption impact of x's. A theoretical framework is developed to guide the cost-effective synthesis of multi-modal compactor that can deliver x-mitigation capabilities in every mode it operates. Adaptiveness of the proposed response compactor enhances the observability of scan cells cost-effectively, where observability enhancements can be tailored in a fault model-dependent or -independent manner, in either way improving test quality and/or test costs.

Unified 2-D X-Alignment for Improving the Observability of Response Compactors

Despite the advantages of performing response compaction in integrated-circuit testing, unknown response bits (x's) inevitably reflect into loss in test quality. The distribution of these x's within the captured response, which varies for each test pattern, directly impacts the number of scan cells observed through the response compactor. In this paper, we propose a unified 2-D x-alignment technique in order to judiciously manipulate the distribution of x's in the test response prior to its compaction. The controlled response manipulation is performed on a per pattern basis, in the form of scan chain delay and intra-slice rotate operations, and with the objective that x's are aligned within as few scan slices and chains as possible. Consequently, a larger number of scan cells are observed after compaction for any test pattern. In an effort to tackle the unified 2-D x-alignment problem and to achieve maximum overall observability, we first decipher the interaction between 1-D x-alignment operations, and formulate 1-D and 2-D x-alignment operations all as maximum satisfiability (MAX-SAT) problems; a weighted MAX-SAT formulation is necessitated in the 2-D case to identify the best possible 2-D x-alignment, which may differ from back to back application of the individual best possible 1-D alignments in two dimensions. The proposed technique is test set independent, leading to a generic, simple, and cost-effective hardware implementation. While we show in this paper that x-alignment improves horizontal and vertical compactors, covering a wide spectrum of compactors, it is expected to improve other types of compactors as well by manipulating the x-distribution properly.

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal--spatial and time--signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.

On Compaction Utilizing Inter and Intra-Correlation of Unknown States

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Unknown (X) states are increasingly often identified as having potential for rendering semiconductor tests useless. One of the key requirements for a reliable test response compactor is, therefore, to preserve observability of any scan cell for a wide range of X-profiles while maintaining very high-compaction ratios, providing ability to detect a variety of failures found in real silicon, and assuring design simplicity. We have proposed a fully X-tolerant test response compaction scheme which is based on a flexible scan chain selection mechanism. This new approach delivers extremely high compression of test results by observing that X states are typically not randomly distributed in test responses. Identical or similar patterns of correlated X states let the proposed scheme reduce the size of a scan chain selector and the amount of test data used to control it. It handles, moreover, a wide range of unknown state profiles such that all X states, including those being clustered and of high density, are suppressed in a per-cycle mode without compromising the test quality. </para>

X-Align: Improving the Scan Cell Observability of Response Compactors

While response compaction reduces the size of expected vectors that need to be stored on tester memory, the consequent information loss inevitably reflects into loss in test quality. Unknown x's further exacerbate the quality loss problem, as they mask out errors captured in other scan cells in the presence of response compactors. In this paper, we propose a technique that manipulates the x distribution in scan responses prior to their propagation into the response compactor. A block, which we refer to as x-align, inserted between the scan chains and the response compactor aligns response x's within the same slices as much as possible in order to increase the number of scan cells that can be observed through the compactor. The alignment of x's is achieved by delaying the scan-out operations in the scan chains, wherein the proper delay values are computed judiciously. We present an Integer Linear Programming (ILP) formulation and a computationally efficient greedy heuristic for the computation of the delay values for scan chains. The x-align hardware is generic yet reconfigurable. An analysis of x distribution in a captured response helps compute the proper delay values, with which x-align is reconfigured to maximize the alignment of x's. The scan cell observability enhancement delivered by x-align paves the way for the utilization of simple response compactors, such as parity trees, yet providing high levels of test quality even in the presence of a large density of response x's. X-align can also be utilized with any response compactor to manipulate the x distribution in favor of the compactor, thus improving the test quality attained.

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction

This paper presents a novel X-handling technique, which removes the effect of unknowns on compacted test response with maximal compaction ratio. The proposed method combines with the current X-tolerant compactors and inserts masking cells on scan paths to selectively mask X's. By doing this, the number of unknown responses in each scan-out cycle could be reduced to a reasonable level such that the target X-tolerant compactor would tolerate with guaranteed possible error detection. It guarantees no test loss due to the effect of X's, and achieves the maximal compaction that the target response compactor could provide as well. Moreover, because the masking cells are only inserted on the scan paths, it has no performance degradation of the designs. Experimental results demonstrate the effectiveness of the proposed method.

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss

This paper presents a unified test compression technique for scan stimulus and unknown masking data with seamless integration of test generation, test compression and all unknown response masking for high quality manufacturing test cost reduction. Unlike prior test compression methods, the proposed approach considers the unknown responses during test pattern generation procedure, and then selectively encodes the less specified bits (either 1s or 0s) in each scan slice for compression while at the same time masks the unknown responses before sending them to the response compactor. The proposed test scheme could dramatically reduce test data volume as well as the number of required test channels by using only c tester channels to drive N internal scan chains, where c = [log2N] + 2. In addition, because all the unknown responses could be exactly masked before entering into the response compactor, test loss due to unknown responses would be eliminated. Experimental results on both benchmark circuits and larger designs indicated the effectiveness of the proposed technique.

Scan Architecture With Align-Encode

Scan architectures that provide compression capabilities have become mandatory due to the unbearable test costs imposed by high test data volume and prolonged test application. To alleviate these test costs, a stimulus decompressor and a response compactor block are inserted between the tester channels and the scan chains. As a result, a few tester channels drive a larger number of scan chains. In such an architecture, whether a particular test pattern can be delivered depends on the care bit distribution of that pattern. In this paper, we introduce a hardware block to be utilized in conjunction with a combinational stimulus decompressor block. This block, namely, Align-Encode, provides a deterministic per pattern control over care bit distribution of test vectors, improving pattern deliverability, and thus, the effectiveness of the particular stimulus decompressor. Align-Encode is reconfigured on a per pattern basis to delay the shift-in operations in selected scan chains. The number of cycles that a chain may be delayed can be between zero and the maximum allowable value, in order to align the scan slices in such a way that originally undeliverable test vectors become encodable. The reconfigurability of Align-Encode provides a test pattern independent solution, wherein any given set of test vectors can be analyzed to compute the proper delay information. We present efficient techniques for computing the scan chain delay values that lead to pattern encodability. Experimental results also justify the test pattern encodability enhancements that Align-Encode delivers, enabling significant test quality improvements and/or test cost reductions.

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis

This article describes a two-stage test response compactor with an overdrive section, scan chain selection logic, and an on-chip comparator and registration scheme for efficient signature-based diagnosis. This solution offers compaction ratios much higher than those determined by the ratio of scan chains to compactor outputs, and it guarantees very good observability and diagnostic resolution of scan errors, even for a large number of Xs. Experimental results confirm that the proposed solution does not compromise test quality and requires a minimal amount of information to control the compactor itself.