Abstract

Test output compactors can effectively reduce the data volume of test responses without scarifying fault coverage. However, when there are unknown values (X-bits) in the test output, the fault coverage can be severely comprised. Many compaction schemes that can handle X-bits have been developed. However, existing test response compaction schemes are designed without considering the locations of errors and X-bits. This design methodology essentially assumes that observable errors as well as X-bits are randomly distributed among all scan cells. Recent studies show that X-bits may not be randomly distributed; some scan cells could capture much more X-bits than others. In this paper, we propose to exploit the nonuniform distribution of X-bits to optimize test response compactors such that a higher compression rate is achieved with lower hardware overhead. The proposed design method is applicable to various test output compaction schemes that can handle X-bits in the test responses, including X-blocking, X-masking, and X-tolerant circuits. Experimental results show that, in the presence of X-bits, the compression results will be significantly improved with the help of the proposed method.

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