Abstract
The paper presents the use of Genetic Algorithm to search for non-linear Autonomous Test Structures (ATS) in Built-In Testing approach. Such structures can include essentially STP and CSTP and their modifications. Non-linear structures are more difficult to analyze than the widely used structures such as independent Test Pattern Generator and the Test Response Compactor realized by Linear Feedback Shift Registers. To reduce time-consuming test simulation of sequential circuit, it was used an approach based on the stochastic model of pseudo-random testing. The use of stochastic model significantly affects the time effectiveness of the search for evolutionary autonomous structures. In test simulation procedure, the block of sequential circuit memory is not disconnected. This approach does not require a special selection of memory registers such as BILBOs. A series of studies to test circuits set ISCAS’89 are made. The results of the study are very promising.
Highlights
Digital systems should provide services according to the specifications reliably
These structures can be implemented in Field Programmable Gate Arrays (FPGA) [5], Application Specific Integrated Circuit (ASIC), System-on-Chip (SOC), Vietnam Journal of Computer Science (2018) 5:263–278 which consist of many virtual Intellectual Property modules (IP Core)
Statistical analysis of the results showed a correlation from low to strong, between the length of the sequences and Fault Coverage (FC) for the specified Autonomous Test Structures (ATS) structures
Summary
Digital systems should provide services according to the specifications reliably. Impairments of dependability are associated with a large class of faults, errors and failures. The Circuit Under Test (CUT) in non-linear technique is a feedback of STP or CSTP, posing a problem with parameter selection for these structures. These structures can be implemented in Field Programmable Gate Arrays (FPGA) [5], Application Specific Integrated Circuit (ASIC), System-on-Chip (SOC), Vietnam Journal of Computer Science (2018) 5:263–278 which consist of many virtual Intellectual Property modules (IP Core). It should be noted that both in linear and non-linear testing techniques, the circuit MM is typically included into self-testing structure registers as results from ability to improve testability and application of Design for Testability (DFT). The paper is an extended version of a previously published article titled “Genetic Algorithm for Self-Test Path and Circular Self-Test Path Design” that was presented at ACIIDS 2017 conference [7]
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
