Resource Overhead Research Articles

Low-overhead code concatenation approaches for universal quantum computation

Fault-tolerant quantum circuit design can be done by using a set of transversal gates. However, as there is no quantum error correction code with a universal set of transversal gates, several approaches have been proposed which, in combination of transversal gates, make universal fault-tolerant quantum computation possible. Magic state distillation, gauge fixing, code switching, code concatenation and pieceable fault tolerance are well-known examples of such approaches. However, the overhead of these approaches is one of the main bottlenecks for large-scale quantum computation. In this paper, two approaches for universal fault-tolerant quantum computation, mainly based on code concatenation, are proposed. The first approach combines the code concatenation approach with code switching, pieceable fault tolerance or magic state distillation and the second approach extends the nonuniformity of the concatenated codes by allowing to apply CNOT gates between different codes. The proposed approaches outperform the code concatenation approach in terms of both number of qubits and code distance and have also significantly less resource overhead than magic state distillation. This is achieved at the cost of reducing the effective distance of the concatenated code for implementing non-transversal gates.

A novel blind spatial-based random access to pilots (BSB-RAP) in overloaded massive MIMO systems

In this study, to increase the success rate of active user admission in overloaded massive multi-input multi-output (MIMO) systems, a new spatially based random access to pilots (RAP) is proposed to assign orthogonal pilots to the users requesting network access. Therefore, by increasing the acceptance rate of users in a cell, this approach reduces the training overhead and waste of resources. In the massive MIMO for crowd scenarios, the main issue is the limited number of available orthogonal pilots employed by the users in the channel estimation process. This novel approach as spatially based random access enables us to have more connected users during every coherence interval (CI) despite the mentioned limitation. Intrinsic angular domain sparsity of massive MIMO channels and the sporadic traffic of users can help us obtain the spatial features of active UEs in a blind continuous compressed sensing (CCS) approach. Proposed approach is to use a continuous compressed sensing technique based on a prior optimization that provides users’ angle of arrival (AoA) and an innovative space-based RAP protocol to assign orthogonal pilots to active users in coherent transmission. Unlike the previous works, this strategy does not need to limit the number of users to the number of available orthogonal pilots due to the employed spatial degrees of freedom.

Realizing credible remote agricultural auditing with trusted video technology

Abstract The conventional approaches of auditing agricultural commodities from the production and transportation level to the retailers and consumers often get obstructed by the lack of human resources, delayed response, and high frequency of location updates—resulting in poor quality and safety compliance. Its digital transformation, known as remote auditing, could address these limitations to a greater extent; however, it is still subject to diverse cyberattacks, including tampering with the video streams provided for verification. Since a detailed and concurrent forensic examination of videos during remote auditing significantly increases the computational burden on the network and infrastructure, alternative or complementary solutions should be developed. This paper outlines the technical feasibility of applying digital signatures over live video streams as a way to authenticate the source during remote auditing and thus contributes to limiting the scope of potential cyber threats. It proposes design options for realizing the authentication process with trusted computing technologies at different phases, from signing the videos to transmitting them through unreliable networks. A reference prototype is also developed based on the proposed end-to-end design to quantify the performance of trusted remote agricultural auditing in terms of the frame signing time, attack resistance, and resource overhead.

Low-Cost Shuffling Countermeasures Against Side-Channel Attacks for NTT-Based Post-Quantum Cryptography

Lattice-based cryptography (LBC) schemes are promising candidates in the post-quantum cryptography (PQC) standardization process. Number theoretic transform (NTT), as a crucial technique, is widely used to accelerate LBC implementations on computer systems. However, existing side-channel attacks can recover the secret key in real-world cryptographic devices bypassing mathematical problems. The motivation of this work is to provide a low-cost security-enhanced architecture for NTT-based PQC processors. We convert the nested loops in NTT to a hardware-friendly single-level loop. The corresponding architecture instantiates a unified shuffling controller to schedule the order of independent basic operations. We propose the coefficient index randomization and the NTT network randomization schemes against existing power attacks and template attacks. We further achieve high performance and efficiency on the off-the-shelf FPGAs. The shuffling schemes have a negligible impact on performance, and the resource overhead is only 9%.

A Channel Pruning Optimization With Layer-Wise Sensitivity in a Single-Shot Manner Under Computational Constraints

In the constrained computing environments such as mobile device or satellite on-board system, various computational factors of hardware resource can restrict the processing of deep learning (DL) services. Recent DL models such as satellite image analysis mainly require larger resource memory occupation for intermediate feature map footprint than the given memory specification of hardware resource and larger computational overhead (in FLOP) to meet service-level objective in the sense of hardware accelerator. As one of the solutions, we propose a new method of controlling the layer-wise channel pruning in a single-shot manner that can decide how much channels to prune in each layer by observing dataset once without full pretraining. To improve the robustness of the performance degradation, we also propose a layer-wise sensitivity and formulate the optimization problems for deciding layer-wise pruning ratio under target computational constraints. In the paper, the optimal conditions are theoretically derived, and the practical optimum searching schemes are proposed using the optimal conditions. On the empirical evaluation, the proposed methods show robustness on performance degradation, and present feasibility on DL serving under constrained computing environments by reducing memory occupation, providing acceleration effect and throughput improvement while keeping the accuracy performance.

Hardware-Supported Patching of Security Bugs in Hardware IP Blocks

To satisfy various design requirements and application needs, designers integrate multiple intellectual property blocks (IPs) to produce a system on chip (SoC). For improved survivability, designers should be able to patch the SoC to mitigate potential security issues arising from hardware IPs; for increased flexibility, we propose adding programmable hardware-based support for monitoring and bug mitigation. However, it is a challenge to decide how much additional cost a designer should expend up front to deal with unknown, future issues. We propose an approach that guides designers toward maximizing the benefits of adding “patchability” to various IPs in the system, given a target resource overhead. We frame the design problem as an integer quadratic program and show that our approach achieves superior patchability compared to the naïve and baseline approaches for a given cost limit. Experimental results show that when we set a cost limit of 2% field-programmable gate array adaptive logic module usage, our solution can generate a viable patching infrastructure with six patching blocks offering patches for seven different services in our case study.

Dynamic Rapid Scheduling Algorithm for Vehicle Time Sensitive Communication based on CILP and AGA

Vehicle time-sensitive communication (VTSC) is an emerging paradigm where the Time-Sensitive Networking together with V2X provides connected vehicle with deterministic and low communication latency. Scheduling is a critical step to realize the determinism. Recently, as the scale and variety of VTSCs increase, the requirements of simultaneously achieve multicast supportment, short runtime, dynamic schduling ability and low resource overhead challenge the traditional TSN scheduling algorithms. This paper proposes a scheduling scheme with multiple stages to achieve both efficient and rapid scheduling. This paper first formulates the joint routing and scheduling problems by proposing a cluster-Integer Linear Programming (CILP). It aims to accelerate the static scheduling and realize real-time response for dynamic incremental scheduling. An improved topology pruning method and a clustering-aggregation ILP procedure are presented. Then, since the dynamic scheduling will gradually reduce the resource utilization, this paper proposes an adaptive genetic algorithm (AGA) to rapidly perform the resource optimization. The crossover operator, mutation operator, adaptive probability and fitness function are designed, supporting multicast TSN flows. Finally, this paper conducts extensive simulations to validate the proposed algorithms. The results show that, comparing with traditional methods, the proposed CILP method can reduce the average runtime by up to 86.7% for static scheduling and realize real-time dynamic scheduling. The proposed AGA method can reduce the resource optimization runtime by up to 70% while improving the schedulability. The overall multi-stage scheduling mechanism could satisfy the VTSC scheduling requirements.

Efficient diagnostics for quantum error correction

Fault-tolerant quantum computing will require accurate estimates of the resource overhead under different error correction strategies, but standard metrics such as gate fidelity and diamond distance have been shown to be poor predictors of logical performance. We present a scalable experimental approach based on Pauli error reconstruction to predict the performance of concatenated codes. Numerical evidence demonstrates that our method significantly outperforms predictions based on standard error metrics for various error models, even with limited data. We illustrate how this method assists in the selection of error correction schemes.

Construction of bias-preserving operations for pair-cat codes

Fault-tolerant quantum computation with depolarization error often requires demanding error threshold and resource overhead. If the operations can maintain high noise bias---dominated by dephasing error with small bit-flip error---we can achieve hardware-efficient fault-tolerant quantum computation with a more favorable error threshold. Distinct from two-level physical systems, multilevel systems (such as harmonic oscillators) can achieve a desirable set of bias-preserving quantum operations while using continuous engineered dissipation or Hamiltonian protection to stabilize to the encoding subspace. For example, cat codes stabilized with driven-dissipation or Kerr nonlinearity can possess a set of bias-preserving gates while continuously correcting bosonic dephasing error. However, cat codes are not compatible with continuous quantum error correction against excitation loss error, because it is challenging to continuously monitor the parity to correct photon loss errors. In this work, we generalize the bias-preserving operations to pair-cat codes, which can be regarded as a multimode generalization of cat codes, to be compatible with continuous quantum error correction against both bosonic loss and dephasing errors. Our results open the door towards hardware-efficient robust quantum information processing with both bias-preserving operations and continuous quantum error correction simultaneously correcting bosonic loss and dephasing errors.

Load Estimation Based Dynamic Access Protocol for Satellite Internet of Things

In recent years, the Internet of Things (IoT) industry has become a research hotspot. With the advancement of satellite technology, the satellite Internet of Things is further developed along with a new generation of information technology and commercial markets. However, existing random access protocols cannot cope with the access of a large number of sensors and short burst transmissions. The current satellite Internet of Things application scenarios are divided into two categories, one has only sensor nodes and no sink nodes, and the other has sink nodes. A time-slot random access protocol based on Walsh code is proposed for the satellite Internet-of-Things scenario with sink nodes. In this paper, the load estimation algorithm is used to reduce the resource occupancy rate in the case of medium and low load, and a dynamic Walsh code slot random access protocol is proposed to select the appropriate Walsh code length and frame length h. The simulation results show that the slotted random access protocol based on Walsh code can effectively improve the throughput of the system under high load. The introduction of load estimation in the case of medium and low load can effectively reduce the resource utilization of the system, and ensure that the performance of the access protocol based on Walsh codes does not deteriorate. However, in the case of high load, a large resource overhead is still required to ensure the access performance of the system.

The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System

The multi-FPGA system known as, the Flow-in-Cloud (FiC) system, is composed of mid-range FPGAs that are directly interconnected by high-speed serial links. FiC is currently being developed as a server for multi-access edge computing (MEC), which is one of the core technologies of 5G. Because the applications of MEC are sometimes timing-critical, a static time division multiplexing (STDM) network has been used on FiC. However, the STDM network exhibits the disadvantage of decreasing link utilization, especially under light traffic. To solve this problem, we propose a hybrid router that combines packet switching for low-priority communication and STDM for high-priority communication. In our hybrid network, the packet switching uses slots that are unused by the STDM; therefore, best-effort communication by packet switching and QoS guarantee communication by the STDM can be used simultaneously. Furthermore, to improve each link utilization under a low network traffic load, we propose a dynamic communication switching algorithm. In our algorithm, each router monitors the network load metrics, and according to the metrics, timing-critical tasks select the STDM according to the metrics only when congestion occurs. This can achieve both QoS guarantee and efficient utilization of each link with a small resource overhead. In our evaluation, the dynamic algorithm was up to 24.6% faster on the execution time with a high network load compared to the packet switching on a real multi-FPGA system with 24 boards.

Feasibility of critical infrastructure protection using network functions for programmable and decoupled ICS policy enforcement over WAN

Industrial control systems (ICS) represent a major component of our critical infrastructure. With the increasing need for more control and monitoring of such systems, ICS have seen an increase in connectivity to wide area networks (WAN) exposing aging equipment to rapidly evolving cybersecurity threats. Furthermore, the ICS data requires a reliability measure from the networks for critical functions for infrastructure monitoring and control. Especially when remote plant sites are involved such as pipelines, energy distribution networks, and transportation, WAN transport impairments most often provide a best effort delivery with no strict reliability guarantees. Network functions can provide a vendor agnostic, programmable critical infrastructure protection with a single maintenance, policy determination, and reliability assurance surface. A network function (NF) can be utilized for policy enforcement over the communication between remote entities and the main control office. This paper presents the research on transparent integration with existing ICS without disrupting communications, resulting in minimal downtime while decoupling the fast paced evolution of defensive security measures from the upgrade cycle of expensive long term hardware. We report our measurements on the resource requirements and overhead in the network for successful NF insertion under a wide variety of network impairments (network packet delay, reordering, and loss). Our paired NF implementation provides a policy enforcement platform extensible to cover myriad cybersecurity-related communication goals, including packet signing for verification, encryption for data privacy, packet filtering and data diode operation (i.e. protecting against eavesdropping, packet injection, and denial-of-service). Furthermore, bundling communication specifications into packet flows allows for tunability in applying policies as coarse- or fine-grained as the needs of the operator. We report on network function resource requirements in the form of required queue depth and network utilization overhead.

SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme.

Deep neural networks have been deployed in various hardware accelerators, such as graph process units (GPUs), field-program gate arrays (FPGAs), and application specific integrated circuit (ASIC) chips. Normally, a huge amount of computation is required in the inference process, creating significant logic resource overheads. In addition, frequent data accessions between off-chip memory and hardware accelerators create bottlenecks, leading to decline in hardware efficiency. Many solutions have been proposed to reduce hardware overhead and data movements. For example, specific lookup-table (LUT)-based hardware architecture can be used to mitigate computing operation demands. However, typical LUT-based accelerators are affected by computational precision limitation and poor scalability issues. In this paper, we propose a search-based computing scheme based on an LUT solution, which improves computation efficiency by replacing traditional multiplication with a search operation. In addition, the proposed scheme supports different precision multiple-bit widths to meet the needs of different DNN-based applications. We design a reconfigurable computing strategy, which can efficiently adapt to the convolution of different kernel sizes to improve hardware scalability. We implement a search-based architecture, namely SCA, which adopts an on-chip storage mechanism, thus greatly reducing interactions with off-chip memory and alleviating bandwidth pressure. Based on experimental evaluation, the proposed SCA architecture can achieve 92%, 96% and 98% computational utilization for computational precision of 4 bit, 8 bit and 16 bit, respectively. Compared with state-of-the-art LUT-based architecture, the efficiency can be improved four-fold.

Semi-HFL: semi-supervised federated learning for heterogeneous devices

In the vanilla federated learning (FL) framework, the central server distributes a globally unified model to each client and uses labeled samples for training. However, in most cases, clients are equipped with different devices and are exposed to a variety of situations. There are great differences between clients in storage, computing, communication, and other resources, which makes unified deep models used in traditional FL cannot fit clients’ personalized resource conditions. Furthermore, a great deal of labeled data is needed in traditional FL, whereas data labeling requires a great investment of time and resources, which is hard to do for individual clients. As a result, clients only have a vast amount of unlabeled data, which goes against the federated learning needs. To address the aforementioned two issues, we propose Semi-HFL, a semi-supervised federated learning approach for heterogeneous devices, which divides a deep model into a series of small submodels by inserting early exit branches to meet the resource requirements of different devices. Furthermore, considering the availability of labeled data, Semi-HFL introduces semi-supervised techniques for training in the above heterogeneous learning process. Specifically, two training phases are included in the semi-supervised learning process, unsupervised learning on clients and supervised learning on the server, which makes full use of clients’ unlabeled data. Through image classification, text classification, next-word prediction, and multi-task FL experiments based on five kinds of datasets, it is verified that compared with the traditional homogeneous learning method, Semi-HFL not only achieves higher accuracies but also significantly reduces the global resource overhead.

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator

Spiking neural networks (SNNs) have been witnessing the developing trends to reduce the model size and improve the hardware efficiency for area- and energy-based applications, which are processed by model pruning and data compressions. However, it is challenging to exploit the unstructured sparsity of SNNs for the dense neuromorphic processors. In this article, we present an efficient sparse SNN accelerator (ESSA), which leverages both the temporal sparsity of spike events and the spatial sparsity of weights in SNN inference. It provides both the compressed weights for sparse SNNs and the uncompressed weights for compact SNNs. The self-adaptive spike compression is proposed for sparse spike scenarios, leading to the improvement of throughput by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.2\times $ </tex-math></inline-formula> . ESSA executes a flexible fan-in–fan-out tradeoff by using combinable dendrites, which overcomes the fan-in limitation in neuromorphic systems. Furthermore, a low-latency intrachip spike multicast method is adopted to reduce the resource overhead. Implemented on the Xilinx Kintex Ultrascale field-programmable gate array (FPGA), ESSA achieves an equivalent performance of 253.1 GSOP/s and an energy efficiency of 32.1 GSOP/W for 75% weight sparsity at 140 MHz. The implementation of a four-layer fully connected SNN is expected to perform <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.6~\mu \text{s}$ </tex-math></inline-formula> per time step and the energy consumption is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$14.6~\mu \text{J}$ </tex-math></inline-formula> . Our results demonstrate that ESSA outperforms several state-of-the-art application-specific integrated circuit (ASIC) or FPGA neuromorphic processors.

Single-shot quantum error correction with the three-dimensional subsystem toric code

Fault-tolerant protocols and quantum error correction (QEC) are essential to building reliable quantum computers from imperfect components that are vulnerable to errors. Optimizing the resource and time overheads needed to implement QEC is one of the most pressing challenges. Here, we introduce a new topological quantum error-correcting code, the three-dimensional subsystem toric code (3D STC). The 3D STC can be realized with geometrically-local parity checks of weight at most three on the cubic lattice with open boundary conditions. We prove that one round of parity-check measurements suffices to perform reliable QEC with the 3D STC even in the presence of measurement errors. We also propose an efficient single-shot QEC decoding strategy for the 3D STC and numerically estimate the resulting storage threshold against independent bit-flip, phase-flip and measurement errors to be pSTC ≈ 1.045%. Such a high threshold together with local parity-check measurements make the 3D STC particularly appealing for realizing fault-tolerant quantum computing.

FLEE: A Hierarchical Federated Learning Framework for Distributed Deep Neural Network over Cloud, Edge, and End Device

With the development of smart devices, the computing capabilities of portable end devices such as mobile phones have been greatly enhanced. Meanwhile, traditional cloud computing faces great challenges caused by privacy-leakage and time-delay problems, there is a trend to push models down to edges and end devices. However, due to the limitation of computing resource, it is difficult for end devices to complete complex computing tasks alone. Therefore, this article divides the model into two parts and deploys them on multiple end devices and edges, respectively. Meanwhile, an early exit is set to reduce computing resource overhead, forming a hierarchical distributed architecture. In order to enable the distributed model to continuously evolve by using new data generated by end devices, we comprehensively consider various data distributions on end devices and edges, proposing a hierarchical federated learning framework FLEE , which can realize dynamical updates of models without redeploying them. Through image and sentence classification experiments, we verify that it can improve model performances under all kinds of data distributions, and prove that compared with other frameworks, the models trained by FLEE consume less global computing resource in the inference stage.

Ground-State Preparation and Energy Estimation on Early Fault-Tolerant Quantum Computers via Quantum Eigenvalue Transformation of Unitary Matrices

Under suitable assumptions, the algorithms in [Lin, Tong, Quantum 2020] can estimate the ground state energy and prepare the ground state of a quantum Hamiltonian with near-optimal query complexities. However, this is based on a block encoding input model of the Hamiltonian, whose implementation is known to require a large resource overhead. We develop a tool called quantum eigenvalue transformation of unitary matrices with real polynomials (QET-U), which uses a controlled Hamiltonian evolution as the input model, a single ancilla qubit and no multi-qubit control operations, and is thus suitable for early fault-tolerant quantum devices. This leads to a simple quantum algorithm that outperforms all previous algorithms with a comparable circuit structure for estimating the ground state energy. For a class of quantum spin Hamiltonians, we propose a new method that exploits certain anti-commutation relations and further removes the need of implementing the controlled Hamiltonian evolution. Coupled with Trotter based approximation of the Hamiltonian evolution, the resulting algorithm can be very suitable for early fault-tolerant quantum devices. We demonstrate the performance of the algorithm using IBM Qiskit for the transverse field Ising model. If we are further allowed to use multi-qubit Toffoli gates, we can then implement amplitude amplification and a new binary amplitude estimation algorithm, which increases the circuit depth but decreases the total query complexity. The resulting algorithm saturates the near-optimal complexity for ground state preparation and energy estimating using a constant number of ancilla qubits (no more than 3).

Multi-Level Over-the-Air Aggregation of Mobile Edge Computing Over D2D Wireless Networks

In this paper, we consider a wireless multihop device-to-device (D2D) based mobile edge computing (MEC) system, where the destination wireless device (WD) is scheduled to compute nomographic functions. Under the MapReduce framework and motivated by reducing communication resource overhead, we propose a new multi-level over-the-air (OTA) aggregation scheme for the destination WD to collect the individual partially aggregated intermediate values (IVAs) for reduction from multiple source WDs in the data shuffling phase. For OTA aggregation per level, the source WDs employ a truncated channel-inverse structure multiplied by their individual transmit coefficients in transmission over the same time-frequency resource blocks, and the destination WD finally uses a receive filtering factor to construct the aggregated IVA. Under this setup, we develop a unified transceiver design framework that minimizes the mean squared error (MSE) of the aggregated IVA at the destination WD subject to the source WDs’ individual power constraints, by jointly optimizing the individual transmit coefficients of the source WDs and the receive filtering factor of the destination WD. The formulated power-constrained MSE minimization problem is non-convex. First, based on the primal decomposition method, we derive the closed-form solution under the special case of a common transmit coefficient. This shows that the common transmit coefficient of the source WDs is determined by the minimal transmit power budget among them. Next, for the general case, we transform the original problem into a quadratic fractional programming problem, and then develop a low-complexity algorithm to obtain the (near-) optimal solution by leveraging Dinkelbach’s algorithm along with the Gaussian randomization method. Numerical results are provided to demonstrate the significant performance gains achieved by the proposed multi-level OTA aggregation scheme over various existing schemes.

Review of bio-inspired optimization applications in renewable-powered smart grids: Emerging population-based metaheuristics

The management of renewable-powered smart grids deals with nonlinear optimization problems featuring a variety of linear or nonlinear constraints, discrete or continuous optimization variables, involving high dimensionality of the solution space, and strict time requirements to identify the optimal or near-optimal solution. One promising approach for addressing such optimization problems is to apply bio-inspired population-based optimization algorithms, many such metaheuristics emerging lately. In this paper, we have identified the metaheuristics with the highest impact published recently and reviewed their applications in the management of renewable-powered smart energy grids using the Preferred Reporting Items for Systematic reviews and Meta-Analyses (PRISMA) methodology and the Web of Science Core Collection as the reference database. Four main smart grid application domains we been analyzed: (i) energy prediction models’ optimization to reduce uncertainty (ii) energy resources coordination to handle the stochastic nature of renewables, (iii) demand response using controllable loads and flexibility while considering the consumers’ needs and constraints and (iv) optimization of grid energy efficiency and costs. The results showed the advantages of such metaheuristics for decentralized optimization problems with low computational time and resource overhead. At the same time, several issues need to be addressed to increase their adoption in the smart grid management scenarios: the lack of standard testing methodologies and benchmarks, efficient management of exploration and exploitation of the optimization search space, guidelines for metaheuristics application with clear links to the type of optimization problems, etc.