Resistor Test Structures Research Articles

Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

MeV level aluminum implants into 4H-SiC were performed as part of superjunction diode fabrication. Measurement of resistance test structures produced resistivities well above expected values with large decreases at elevated temperatures. Capacitance-voltage measurements indicate a high activation rate of the implanted aluminum. Temperature dependent Hall measurements produce reasonable hole mobilities with acceptor ionization energies of approximately 330meV, well above the 200meV expected for low concentration aluminum doping in 4H-SiC.

Experimental verification of internal resistance models for PERT-type solar cells

We present different models for the internal resistance of passivated emitter and rear totally diffused (PERT) solar cells. First we apply the model of Gelmont and Shur for the spreading resistance of a passivated emitter and rear cell (PERC) structure with line-shaped contacts and adapt this model to account for the elliptic contact shape of Al-alloyed contacts. To account for the additional vertical current flow through the silicon wafer and the lateral current flow through the back surface field (BSF) of a PERT structure, we evaluate an alternative model using the analogy to the transfer length method (TLM) problem. For experimental verification, we have fabricated resistance test structures for various wafer resistivities, BSF doping levels and line distances (finger pitches) of the line-shaped contacts. Our experimental data shows good agreement with the presented models in distinct parameter ranges and thus offers a solid basis for analytical modelling of PERT-type solar cells.

Circular test structures for determining the specific contact resistance of ohmic contacts

Though the transport of charge carriers across a metal-semiconductor ohmic interface is a complex process in the realm of electron wave mechanics, such an interface is practically characterised by its specific contact resistance. Error correction has been a major concern in regard to specific contact resistance test structures and investigations by finite element modeling demonstrate that test structures utilising circular contacts can be more reliable than those designed to have square shaped contacts as test contacts become necessarily smaller. Finite element modeling software NASTRAN can be used effectively for designing and modeling ohmic contact test structures and can be used to show that circular contacts are efficient in minimising error in determining specific contact resistance from such test structures. Full semiconductor modeling software is expensive and for ohmic contact investigations is not required when the approach used is to investigate test structures considering the ohmic interface as effectively resistive.

Piezoresistivity of n-type conductive ultrananocrystalline diamond

Recent developments of a piezoresistive sensor prototype based on n-type conductive ultrananocrystalline diamond (UNCD) are presented. Samples were deposited using hot filament chemical vapor deposition (HFCVD) technique, with a gas mixture of H2, CH4 and NH3, and were structured using multiple photolithographic and etching processes. Under controlled deposition parameters, UNCD thin films with n-type electrical conductivity at room temperature (5×10−3–5×101S/cm) could be grown. Respective piezoresistive response of such films was analyzed and the gauge factor was evaluated in both transverse and longitudinal arrangements, also as a function of temperature from 25°C up to 300°C. Moreover, the gauge factor of piezoresistors with various sheet resistance values and test structure geometries was evaluated. The highest measured gauge factor was 9.54±0.32 at room temperature for a longitudinally arranged piezoresistor with a sheet resistance of about 30kΩ/square. This gauge factor is well comparable to that of p-type boron doped diamond; however, with a much better temperature independency at elevated temperatures compared to the boron-doped diamond and silicon. To our best knowledge, this is the first report on piezoresistive characteristics of n-type UNCD films.

Nanometer Interconnect Test Structure for Modeling of Process Variation

With the interconnection density and doubling the number of layers in VLSI, Interconnect line width,pitch,and the thickness of the dielectric layer will changed within the same chip caused by the process variation. and the interconnect parasitics changes ultimately affect circuit performance and yield.IC designers need an accurate BEoL corner model to help circuit design. Standard Interconnect Performance Parameters (SIPPs) is standard method to measure ultra-large scale integrated circuit BEOL performance. Designed parallel plate, layer-skipping parallel plate, comb meander, comb meander for via resistance test structures to extract SIPPs according to their sensitivity differences to different test structures, and realized them in CIF format file with High-level Perl language automatically. Then change to GDSII format file that wafer used widely by Cadence layout software, and pass electrical rule checks. Greatly improved the efficiency of test structure’s design and realized. Lay the foundations for formulation of Design for Manufacturability physical design rules and further research interconnection statistical models under nanometer technology with more unique physical phenomena.

Contact end resistance test structure applied for nanocontact measurements

Graphical abstractDisplay Omitted Highlights? An accurate method to characterize nanoobject-metal line contacts is presented. ? The contact end resistance test structure is adapted from microelectronics. ? The measurement of an individual nanocontact is allowed. ? Contact resistivity allows prediction of contact resistance for any contact size. This paper presents an accurate method and test structure to evaluate ohmic nanocontacts. The procedure permits the characterization of the contact resistance between standard-in-microtechnology interconnect lines and a certain nanoscaled-in-width object. It is based on the adaption of the classic contact end resistance structure used for the measurement of the contact end resistance in microelectronic technologies. After the theoretical model study, the methodology is validated for the single-walled carbon nanotube case.

Interface Characterization of Metals and Metal-nitrides to Phase Change Materials

ABSTRACTWe have investigated the interfacial contact properties of the CMOS compatible electrode materials W, TiW, Ta, TaN and TiN to doped-Sb2Te phase change material (PCM). This interface is characterized both in the amorphous and in the crystalline state of the doped-Sb2Te. The electrical nature of the interface is characterized by contact resistance measurements and is expressed in terms of specific interfacial contact resistance (ρC). These measurements are performed on four-terminal Kelvin Resistor test structures. Knowledge of the ρC is useful for selection of the electrode in the integration and optimization of the phase change memory cells.

Use of Neural Network to Model the Refractive Property of PECVD Silicon Nitride Films used to Prevent Water Permeability of Piezoresistive Pressure Sensor

A plasma-enhanced chemical vapor deposition (PECVD) silicon nitride is used for the passivation layer of ICs and sensors. For example, in blood pressure sensor, the piezoresistive pressure sensor is immerged into liquid and the silicon nitride film is expected to prevent water permeability into it. In this paper, we first applied a design of experiment (DOE) and neural network to discover the relationship between input parameters and refractive indexes of PECVD silicon nitride films. Later we introduced the metrology developed to quantify the water permeability into the film based on the resistance test structure measurement and the break down measurement. These two performance tests could further use to identify the optimal silicon nitride deposition recipe which could prevent water permeability of piezoresistive pressure sensor.

Interfacial Resistive Properties of Nickel Silicide Thin Films to Doped Silicon

Improved means of electrical access to nanotechnology devices and accurate nanoscale characterization of electrical properties of ultrathin layers constituting such electrical contacts is of utmost interest to nanoelectronics researchers. This paper reports on the characterization of interfacial resistive properties of ohmic contacts to doped silicon, incorporating thin films of nickel silicide. Silicon doping was achieved by carefully designed ion implantation of antimony (for n-type) and boron (for p-type). Cross Kelvin resistor test structures were used to extract the specific contact resistivity (SCR) values for the different ohmic contacts fabricated. SCR values, which are quantitative characteristics of interfacial resistive properties, as low as for contacts to antimony-doped silicon and to boron-doped silicon were estimated. These experimental results, representing the lowest such values measured, were based on a rigorous evaluation technique and verified by finite element modeling.

Interfacial Resistive Properties of Multi-layered Silicon-based Ohmic Contacts

AbstractThis article reports on the characterization of two- and three-layer ohmic contacts comprising of titanium disilicide and nickel silicide. Cross Kelvin resistor test structures were used to extract the specific contact resistivity (SCR) values for the different ohmic contacts fabricated. The SCR of aluminum to titanium silicide (Al-TiSi2) ohmic contacts was evaluated to be as low as 6.0 x 10-10 Ωcm2. Three-layer ohmic contacts were created using aluminum and nickel silicide thin films and doped silicon. SCR values as low as 5.0 x 10-9 Ωcm2 to antimony-doped silicon and 3.5 x 10-9 Ωcm2 to boron-doped silicon were evaluated.

Analytical and Finite-Element Modeling of a Cross Kelvin Resistor Test Structure for Low Specific Contact Resistivity

Various test structures have been employed to determine the specific contact resistivity (rho <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</i> ) of ohmic contacts, and cross Kelvin resistor (CKR) test structures are most suitable for estimating low rho <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</i> values. The value determined by CKRs includes error due to parasitic resistances that have been difficult to account for when rho <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</i> is low (< 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> Omega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). In this paper, an analytical technique for determining the error in measurements from CKR test structures is presented. The analytical model described for circular contacts is based on Bessel function expressions. Using several contacts of different diameter ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> ) with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</i> les 0.4 ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</i> is the width of the CKR arms), the parasitic resistance can be accurately accounted for by extrapolation of experimental data to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</i> rarr 0. Finite-element modeling and experimental results for metal-to-silicide contacts are used to validate the analytical expressions presented.

A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology

In this paper, a simple and nondestructive method of modeling 40-nm interconnects is proposed. Traditional methods based on charge-based capacitance measurement model the interconnects by fitting the capacitance or resistance curves, first by assuming one constant process parameter, such as metal thickness, and then by extracting the metal width, metal spacing, and interlevel dielectric (ILD) thickness from certain test patterns that may therefore result in model inaccuracy while the transmission and scanning electron microscopy methods are both destructive and time consuming. The proposed new methodology directly extracts the metal width based on the metal resistance test structures, and then the metal thickness, metal spacing, and ILD thickness without any presumption. It is also nondestructive and fast, with a model accuracy higher than 95%. Furthermore, with the ensured accuracy of layout parameter extraction, the necessity of an accurate interconnect model in the 40 nm technology and beyond is emphasized.

Accurate Estimation of Low $( ≪ \hbox{10}^{-8}\ \Omega \cdot \hbox{cm}^{2})$ Values of Specific Contact Resistivity

Advancements in nanotechnology have created the need for efficient means of communication of electrical signals to nanostructures, which can be addressed using low resistance contacts. In order to study and estimate the resistance of such contacts or the resistance posed by the interface(s) in such contacts, accurate test structures and evaluation techniques need to be used. The resistance posed by an interface is quantified using its specific contact resistivity (SCR), and although multiple techniques have been utilized, inaccuracies of such techniques in measuring values of SCR lesser than ( < 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> Omega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) have been reported. In this letter, an approach for estimating very low values of SCR (lower than the previously limiting ( < 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> Omega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> )) using a cross Kelvin resistor test structure is demonstrated using aluminum to titanium silicide ohmic contacts, with a minimum estimated SCR value of 6.0 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> Omega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Application of power loss calculation to estimate the specific contact resistance of the screen-printed silver ohmic contacts of the large area silicon solar cells

The establishment of a suitable contact formation methodology is a critical part of the technological development of any metal-to-semiconductor contact structure. Many test structures and methodologies have been proposed to estimate the specific contact resistance (ρc) of the planar ohmic contacts formed on the heavily doped semiconductor surface. These test structures are usually processed on the same wafer to monitor a particular process. In this study, new experimental procedure has been evolved to assess the value of ρc of the screen-printed front silver (Ag) thick-film metal contact to the silicon surface. The essential feature of this methodology is that it is an iteration technique based on the calculation of power loss associated with various resistive components of the solar cell normalized to the unit cell area. Therefore, this method avoids the complexity of making the design of any lay out of a standard contact resistance test structure like transmission line model (TLM) or Kelvin resistor, etc. It was shown that value of specific contact resistance of the order of 1.0 × 10−5 Ω−cm2 is measured for the Ag metal contacts formed on the n+ silicon surface. This value is much lower than the ρc data previously reported for the screen-printed Ag contacts. The sintering process of the front metal contact structure at different furnace setting is carried out to understand the possible wet interaction and metal contact formation as a function of the firing. Therefore, the study is further extended to study the peak firing temperature dependence of the ρc of screen-printed Ag metal contacts. It will help to assess the specific contact resistance of the ohmic contacts as a function of firing temperature of sintering process.

The van der Pauw stress sensor

Piezoresistive sensors fabricated on (100) and (111) silicon surfaces are capable of measuring from four to all six components of the stress state at a point on the surface of an integrated circuit die. Such resistor-based sensors have been successfully designed and fabricated on these wafer planes and have been used successfully for measurement of die stresses in electronic packages by many research teams. In this paper, classical van der Pauw (VDP) structures, traditionally used for sheet resistance measurement, are shown to provide more than three times the sensitivity of standard resistor sensors. A single four-terminal VDP device replaces two resistor rosette elements and inherently utilizes the high-accuracy four-wire resistance measurement method. Theoretical expressions are developed for the change in resistance of the VDP device as a function of the individual stress components resolved in wafer coordinate systems on both the (100) and (111) silicon surfaces, and it is predicted theoretically that VDP devices will exhibit more than three times higher sensitivity to stress than standard resistor sensors. Design, fabrication, and experimental characterization of VDP and resistor test structures are presented for both silicon surfaces, and numerical simulation is used to help resolve discrepancies between theory and experiment. Sources of experimental error are identified, and the 3.16 times sensitivity enhancement of the VDP device is confirmed.

A comparative study of different contact resistance test structures dedicated to the power process technology

This paper presents different contact test structures intended to characterize the metal–semiconductor interface (aluminum–silicon) for power integrated circuits fabricated in the Application Specific Discrete (ASD™) process technologies. For this study, three contact test structures have been selected, transfer length method (TLM), cross bridge Kelvin resistance (CBKR), and contact end resistance (CER). The characterization is achieved by extracting the specific contact resistance ( ρ C) from contact test structures by measuring the contact resistance ( R C). To validate the results, spreading resistance was used to determine the surface doping concentration ( C S) of the diffused layer that gives ρ C from a well know standard abacus. From the experimental results, we conclude that only the TLM test structure is able to give correct values of the specific contact resistance for both n and p type diffused layers that are compatibles with the manufacturer specifications.

Universal Error Corrections for Finite Semiconductor Resistivity in Cross-Kelvin Resistor Test Structures

The Cross-Kelvin Resistor test structure is commonly used for the extraction of the specific contact resistance of ohmic contacts. Analysis using this structure are generally based on a two-dimensional model that assumes zero voltage drop in the semiconductor layer in the direction normal to the plane of the contact. This paper uses a three-dimensional (3-D) analysis to show the magnitude of the errors introduced by this assumption, and illustrates the conditions under which a 3-D analysis should be used. This paper presents for the first time 3-D universal error correction curves that account for the vertical voltage drop due to the finite depth of the semiconductor layer.

Electrical characterization of platinum deposited by focused ion beam

Focused ion beam (FIB) systems are commonly used to image, repair and modify integrated circuits by cutting holes in passivation to create vias or to selectively break metal tracks. The ion beam can also be used to deposit a metal, such as platinum, to create new connections. These techniques are very useful tools for debugging designs and testing possible changes to the circuit without the expense of new mask sets or silicon. This paper presents test structures which can be used to characterize a FIB induced platinum deposition process. Sheet resistance test structures have been fabricated using a FIB tool and the results of testing these structures are presented. The sheet resistance data has been used to fabricate platinum straps with a known resistance. This extends the capability of the focused ion beam system beyond the deposition of simple conducting straps. The design of the test structures has been improved through the use of current flow simulation to investigate the effects of geometry and misalignment on the measurement accuracy. The results of these simulations are also presented.

Patterning of nanometer-scale silicide structures on silicon by ‘direct writing focus ion-beam implantation’

We have developed a new technique for direct patterning and formation of cobalt silicide structures using focused ion beam implantation. This mask-free fabrication technique takes advantage of the influence on the kinetics of ion-beam mixing and properties of thin barrier oxides during silicide line formation. Silicide structures with dimensions of the order of 170 nm were produced on (100) silicon substrates. The process involves the ion implantation of 200 keV As ++ through a thin cobalt film on SiO 2/Si structure. A selective reaction barrier at the Si/Co interface comprising of a thin (∼2 nm) oxide (SiO 2), prevents unwanted reactions with silicon. Ion-beam mixing was instrumental in fracturing of the oxide layer, thereby allowing the migration of metal atoms across the Si/Co boundary for the silicidation reaction to proceed during subsequent rapid thermal anneal treatments. Diffusion controlled reactions advanced rapidly in the implanted areas, requiring a two-step anneal sequence to inhibit reaction elsewhere. A threshold dose of 3×10 15 cm −2 was required for process initiation. Four-terminal resistance test structures were formed for electrical measurements. Resistivity obtained ranged on the order of 12 to 23 μΩ-cm. Application of this method can facilitate a wide variety of silicide structures.

Direct patterning of nanometer-scale silicide structures by focused ion-beam implantation through a thin barrier layer

Recently several new approaches have been proposed to manufacture silicide structures using mask-less techniques. We have developed a new technique for direct patterning and formation of cobalt silicide structures using focused ion-beam (FIB) implantation. Utilizing the effects of ion-beam mixing and properties of thin barrier oxides, silicide lines with dimensions down to 170 nm were produced on (100) silicon substrates using the FIB. The process involves the ion implantation of 200 keV As++ through a cobalt thin film. A thin (∼2 nm) oxide (SiOx) at the Si/Co interface acts as a selective reaction barrier. Ion-beam mixing was instrumental in fracturing of the oxide layer, thereby allowing the silicidation reaction to proceed across the boundary during subsequent rapid thermal anneal treatments. Diffusion controlled reactions advanced rapidly in the implanted areas, while it is inhibited elsewhere. A threshold dose of 3×1015 cm−2 was required for process initiation. Four-terminal resistance test structures were formed for electrical measurements. Reported resistivity was in the range of 12 to 23±1 μΩ cm.