Nanometer Interconnect Test Structure for Modeling of Process Variation

Abstract

With the interconnection density and doubling the number of layers in VLSI, Interconnect line width,pitch,and the thickness of the dielectric layer will changed within the same chip caused by the process variation. and the interconnect parasitics changes ultimately affect circuit performance and yield.IC designers need an accurate BEoL corner model to help circuit design. Standard Interconnect Performance Parameters (SIPPs) is standard method to measure ultra-large scale integrated circuit BEOL performance. Designed parallel plate, layer-skipping parallel plate, comb meander, comb meander for via resistance test structures to extract SIPPs according to their sensitivity differences to different test structures, and realized them in CIF format file with High-level Perl language automatically. Then change to GDSII format file that wafer used widely by Cadence layout software, and pass electrical rule checks. Greatly improved the efficiency of test structure’s design and realized. Lay the foundations for formulation of Design for Manufacturability physical design rules and further research interconnection statistical models under nanometer technology with more unique physical phenomena.