Resistive Compensation Research Articles

Temperature field analysis and compensation improvement of load cell

During the operation of load cell, heat is generated by the strain gauge and the electronics on the PCB board, which leads to temperature gradients within the sensor itself. These temperature gradients are unstable at different ambient temperatures. Compensation inaccuracies can also occur when compensating for sensor measurements at different temperatures This paper proposes a method to change the position of temperature compensation resistors to address errors caused by the temperature field effect of the strain gauge sensor itself. Without affecting the sensor’s strain measurement, the correctness of the proposed method is demonstrated through steady-state thermal simulation results in ANSYS and experimental results, effectively addressing errors caused by unstable temperature gradients during the operation of strain gauge sensors.

A high-linearity SP5T SOI switch with a resistive biasing network and capacitance & resistor compensation technology

A high-linearity SP5T SOI switch with a resistive biasing network and capacitance & resistor compensation technology

Recent Trends on MOSFET based Cascode Current Mirrors: An Analytical Survey

To produce copy of current flowing through active devices, from one end to other end of the circuit, current mirrors (CM) are used irrespective of loading effect. It’s indispensable part of an analog and mixed signal system including wide range of applications. In this paper various cascode current mirror circuits such as, an ultra-high compliance current mirror with low power consumption, a CM with extensive swing, a self-biased CM, and quasi-floating CM circuits are analyzed which includes: speed, power, input and output resistance, bandwidth etc. The comparison shows that ultra-high compliance cascode current mirror utilizes low voltage with relatively high frequency response and consumes less power while super cascode configuration is a good choice to obtain high output impedance for better performance, whereas quasi-floating gate MOS current mirror with resistive compensation can be used to enhance the circuit bandwidth. The various circuits are designed at 250 nm, 180 nm, and 130 nm CMOS technologies for justification of performance.

Reconfigurable Logic Operation Scheme Based on Gate-Tunable CBRAM

The traditional von Neumann architecture features large transfer latency and power dissipation. In-memory computing has been widely investigated in an effort to negotiate this hurdle. Herein, gate-tunable conductive bridge random access memory (GCBRAM) is proposed to construct in-memory computing. GCBRAM has a flexible modulation dimension, which can reduce the sensitivity of the selection of compensation resistors. A reconfigurable logic circuit based on GCBRAM has been developed, and the quantity of compensation resistors has been reduced. A full adder based on a GCBRAM circuit has been demonstrated, and the number of compensation resistors has been minimized compared with previous results using basic logic gates. To the best of our knowledge, full adder based on GCBRAM (six GCBRAM, seven steps) is the most compact form developed to date. This work represents the realization of a new form of in-memory logic with lower hardware costs, which can facilitate the development of in-memory computing.

Self-Supporting Ultrathin DLC/Si3N4/SiO2 for Micro-Pressure Sensor

In this study, we firstly reported a micro-pressure sensor based on self-supporting diamond-like carbon (DLC)/Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> films with total thickness of 785 nm, where the DLC film was fabricated by a facile DC magnetron sputtering process. Particularly, the DLC film was selected as a hybrid sensitive and structural material due to its superior mechanical, piezoresistive properties and stability under harsh environment. Results showed that the sensitivity of the integrated sensor could reach <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.3\,\,\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> /kPa within the pressure range of 0–60 kPa, together with the nonlinearity and the hysteresis was 5.7% FS (full scale) and 0.8% FS, respectively (at 20 °C). Most importantly, without any thermal insulation package, the sensitivity only changed slightly within ±7.0% even the temperature varied dramatically from −20 °C to 100 °C. Such excellent performance of the sensor was mainly originated from the good stability of atomic bond structure in DLC films, which was confirmed by the variable-temperature XPS test. In addition, the signal could be further compensated by the DLC thermal compensation resistor in which the temperature coefficient of resistance (TCR) was about −1247.3 ppm/°C. These results bring forward a promising strategy to fabricate the micro-pressure sensor with high structural sensitivity, stability as well as lightweight design for micro-electromechanical system (MEMS) used in harsh applications.

Extended Bandwidth Method on Symmetrical Operational Transconductance Amplifier and Filter Application

In this paper, a symmetrical operational transconductance amplifier (OTA) circuit with extended bandwidth using resistive compensation technique is proposed. Into the all current mirrors of the symmetrical OTA circuit, this technique is applied. A passive resistor is connected between the gate and the drain of each primary transistor of the current mirrors in the symmetrical OTA structure. In addition, filter structures are realized in order to analyze the performance of the symmetrical OTA with extended bandwidth. Thus, the advantage of using resistive compensation technique is demonstrated. The symmetrical OTA with extended bandwidth and the filters are simulated with LTSPICE by using TSMC 0.18 μm CMOS process parameters.

Extended Bandwidth Method on Symmetrical Operational Transconductance Amplifier and Filter Application

In this paper, a symmetrical operational transconductance amplifier (OTA) circuit with extended bandwidth using resistive compensation technique is proposed. Into the all current mirrors of the symmetrical OTA circuit, this technique is applied. A passive resistor is connected between the gate and the drain of each primary transistor of the current mirrors in the symmetrical OTA structure. In addition, filter structures are realized in order to analyze the performance of the symmetrical OTA with extended bandwidth. Thus, the advantage of using resistive compensation technique is demonstrated. The symmetrical OTA with extended bandwidth and the filters are simulated with LTSPICE by using TSMC 0.18 μm CMOS process parameters.

Performance Investigation of Carbon Nanotube Based Temperature Compensated Piezoresistive Pressure Sensor

In silicon-based piezoresistive pressure sensor, the accuracy of the sensor is affected mainly by thermal drift and the sensitivity of the sensor varies with the rise in temperature. Here, the temperature effects on the desired representation of the sensor are analysed. Use of smart material Carbon nanotubes (CNT) and a few effective temperature compensation techniques are presented in this study to reduce the temperature effect on the accuracy of the sensor. Resistive compensation employed extra piezoresistors with Negative Temperature Coefficient of Resistivity (TCR) for temperature compensation. The attainment of the desired compensation techniques is highly compatible with the MEMS device fabrication. The compensated pressure sensor is supremacy for pressure measurement with temperature variations. Though various techniques have been suggested and put into actuality with successful attainment, the techniques featuring easy implementation and perfect compatibility with existing schemes are still blooming demanded to design a piezoresistive pressure sensor with perfect comprehensive performance. In this paper, CNT piezoresistive material has been employed as sensing elements for pressure sensor and compared with silicon in terms of output voltage and sensor performance degradation at higher temperature. Pressure sensors using CNT and silicon piezo resistive sensing materials were simulated on silicon (100) diaphragm by ANYSIS. Based on simulation results, silicon and CNT both pressure sensor also shows better results at near room temperature. With the increasing temperature it is observed that silicon pressure output underestimated by 23%.

High-Speed Low-Power Rail-to-Rail Buffer using Dynamic-Current Feedback for OLED Source Driver Applications

In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer’s first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm $$\times$$ 59 μm).

Four-Quadrant CMOS Analog Current Multiplier Using Frequency Compensation and 1.5 V Supply

This work presents two new CMOS designs of current mode squarer circuits using a 1.5 V supply. The four-quadrant multiplier has also been designed using proposed squarer circuits. To improve bandwidth, the resistive compensation scheme has been exploited. The input and output signals of proposed circuits are of current type and hence exhibit larger dynamic range contrary to voltage mode circuits. Various simulations have been carried out to check performance and validate theoretical analysis. It is observed that range of − 3 dB bandwidth, power consumption and linearity error of the proposed circuits I and II are 542.53 MHz and 1.13 GHz, 0.56 and 0.47 mW and 1.8 and 2%, respectively. In the state of the art, it is noticed that around 10–90% bandwidth is increased while using proposed circuits over most of the conventional circuits. All results are verified using spice tools and 0.18 µm CMOS technology parameters.

A 0.07-mm2 162-mW DAC Achieving &gt;65 dBc SFDR and &lt; −70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing

A digital-to-analog converter (DAC) with small-size non-cascoded current cells is proposed to achieve small area, low-power consumption, and high linearity over a wide bandwidth. An output impedance compensation (OIC) technique using a compensation resistor, implemented by a PMOS with code-dependent gate voltage control, is proposed to remedy the nonlinearity induced by the insufficient output impedance of the non-cascoded current cells. In addition, a proposed concentric parallelogram routing (CPR) technique, in which the subcells of each current cell are arranged such that they form a parallelogram shape with a common centroid, is used to reduce both the mismatch error and the routing-induced timing skew among the current cells. The DAC, implemented in a 28-nm CMOS process, achieves >65-dBc spurious-free dynamic range (SFDR) and < −70-dBc third-order intermodulation distortion (IM3) over the entire Nyquist bandwidth at 10 GS/s while consuming 162 mW from a single 1.1 V supply.

A 150-GHz Transmitter With 12-dBm Peak Output Power Using 130-nm SiGe:C BiCMOS Process

This article presents a compact 150-GHz transmitter with 12-dBm $P_{\mathrm{ sat}}$ and 17-dB conversion gain. This $D$ -band transmitter is composed of a frequency doubler, a micromixer, a two-stage $g_{m}$ -boosting power amplifier (PA), and an on-chip dielectric resonate (DR) antenna. At sub-terahertz, the output power and the gain are the limiting factors for the transmitter’s performance. In this work, $g_{m}$ -boosting topology is implemented to achieve the 17-dB gain by taking advantage of the base inductor without sacrificing the PA’s stability. The output power of the 150-GHz PA is enhanced by the proposed phase compensation method. In this proposed method, an auxiliary inductor is added for adjusting the phase difference to decrease the introduced loss from power combining and matching networks. The imbalance at the LO port is also reduced by the proposed capacitor and the resistor compensation method. From 140 to 160 GHz, the transmitter delivers more than 8-dBm output power, with the maximum $P_{\mathrm{ sat}}$ of 12 dBm at 148 GHz. This transmitter exhibits a conversion gain of 17 dB and an output 1-dB compression point ( ${\mathrm{ OP}}_{1~{\mathrm{ dB}}}$ ) of 11.4 dBm. The transmitter exhibits the highest output power, the highest ${\mathrm{ OP}}_{1~{\mathrm{ dB}}}$ , competitive conversion gain, and bandwidth among any silicon-based transmitters in $D$ -band, to the best of our knowledge.

Compact low‐power 154 GHz receiver front‐end in 0.13 µm SiGe BiCMOS

This study presents a compact 154 GHz receiver fabricated in a 0.13 µm SiGe BiCMOS process, which is composed of a three-stage low-noise amplifier and an improved micromixer. In order to mitigate the intrinsic DC and RF imbalance of the basic micromixer, the resistor compensation is implemented at one branch of the RF paths, which achieves superior performance. Consisting of a common-emitter and two differential cascade stages, the separate low-noise amplifier achieves a small-signal gain of 21.8 dB at 155 GHz with a 3 dB bandwidth of 22 GHz. The entire receiver exhibits a maximum conversion gain of 23.8 dB at 154 GHz with a 3 dB bandwidth of 16.5 GHz. The minimum single-sideband noise figure is measured to be 11.4 dB at 149 GHz and remains below 15 dB from 142 to 160 GHz. Exhibiting high gain, low-noise figure and considerably high bandwidth, the characterised receiver consumes competitive low power of 70.7 mW and occupies the smallest core area of only 0.12 mm 2 to the best of our knowledge.

Low-Voltage Flipped Voltage Follower Cell Based Current Mirrors for High Frequency Applications

The paper proposes low-voltage current mirrors namely low-voltage current mirror (LVCM) and flipped voltage follower based low-voltage current mirror (FVFLVCM) with high bandwidth. The stability of the proposed circuits has been performed by time-domain approach and frequency domain approach using Routh–Hurwitz stability criteria and phase margin calculations, respectively. The bandwidth of the proposed FVFLVCM has also been enhanced using resistive compensation technique. The proposed LVCM and FVFLVCM have wide input current range of 0–100 µA and 0–150 µA, low DC error of 5.9% and 4.9%, low DC power dissipation of 110.39 µW and 99 µW, high bandwidth of 367 MHz and 624 MHz, low input impedance of 16.3 KΩ and 12.3 KΩ, low THD of 0.26% and 1% and low output noise of 2.25 nA and 2.83 nA over 100 MHz, respectively. The results have been simulated using SPICE in the TSMC 0.18 µm CMOS technology and are presented to validate the effectiveness of the proposed current mirrors.

Optimal designs of nulling resistor compensation and a robust bias‐based op‐amp circuit using an evolutionary approach

This article suggests an evolutionary optimisation method namely symbiotic organisms search (SOS) algorithm-based area optimised designs of a nulling resistor compensation circuit and a robust bias-based complementary metal oxide semiconductor (CMOS) analogue operational amplifier (op-amp) circuit. SPICE simulator is used to validate the results obtained by using the optimisation technique SOS. The results obtained by SPICE simulation confirm that all the design specifications are accurately satisfied for both the circuits considered here. The results also prove that the SOS algorithm is superior to the formerly reported methods in terms of the gain, power dissipation, area etc., for both the individual circuits.

Symbiotic organisms search algorithm for optimal design of CMOS two‐stage op‐amp with nulling resistor and robust bias circuit

This study suggests an evolutionary technique namely symbiotic organisms search (SOS) algorithm based optimal designs of two different analogue very-large-scale integration circuits. The configurations considered here are nulling resistor compensation based complementary metal–oxide–semiconductor (CMOS) two-stage op-amp and two-stage CMOS op-amp with robust bias circuit. The prime goal of this work is the sizing of metal–oxide–semiconductor (MOS) transistors employing the SOS algorithm to optimise the area occupied by the individual circuit. Design results based on the SOS algorithm are authenticated with SPICE simulation. SPICE simulation results reveal that all the design specifications are firmly satisfied for both the circuits. Moreover, SPICE based results show that the SOS algorithm provides much better results compared to the earlier reported techniques regarding the gain, MOS area and power dissipation for the abovementioned op-amp circuits.

Digitally tunable active inductor for RF-DCO applications

ABSTRACT The design of a tunable differential active inductor by employing a digitally controlled current source is presented in this work. The design proposes a 4-bit digitally tunable active inductor (DTAI) suitable for multi-band radio frequency-digitally controlled oscillator (RF-DCO) applications. This DTAI has been implemented in standard 180 nm complementary metal–oxide–semiconductor (CMOS) process with a 1.8 V supply, and its performance is analysed. The post-layout simulation results show that DTAI emulates an inductance tuning range of 4 nH to 55 nH with self-resonant frequency ranging from 4.3 GHz to 14.6 GHz. The noise performance of the design along with its power consumption for digital codes [0001 to 1111] is plotted. The maximum quality factor ranges from 4 to 5 without the negative compensation resistor, maximum noise is 1.9 nV/ and maximum power dissipation is 10.5 mW. The layout of the proposed design is drawn, the total area occupied is 48.16 µm x 16.6 µm. An example implementation of the proposed 4-bit DTAI as a DCO targetting RF applications is discussed.

Rotor Resistance Estimation for Induction Machines Using Carrier Signal Injection With Minimized Torque Ripple

This paper presents a technique for estimating the rotor resistance of an induction machine over the machine's entire speed and torque range. This technique is based on injecting a relatively low-frequency carrier signal into the reference of the rotor flux linkage magnitude and extracting the induction machine's response to the carrier signal, which is then used in a model reference adaptive system. This paper also presents a technique to minimize the torque ripple generated by the carrier signal. This technique utilizes the rotor flux linkage reference in conjunction with a proportional-integral-resonant feedback plus feedforward control to generate references for the direct and quadrature axis stator currents. This paper also improves tracking of the torque and rotor flux linkage in direct field-oriented control of the induction machine through employing electromotive force and resistive compensation methods for tracking q-axis and d-axis reference stator currents, respectively. Simulation and experimental results demonstrate the effectiveness of the technique over the entire operating range.

Wide bandwidth CMOS four-quadrant mixed mode analogue multiplier using a second generation current conveyor circuit

This paper presents a new realization for a CMOS four-quadrant analogue multiplier. The proposed circuit is composed of three second generation current conveyor circuits (CCII), two NMOS transistors operating in the linear region, and four passive resistances. It can be operated in current mode and voltage mode without changing the circuit topology. The simulations results of the proposed mixed mode multiplier are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 $\mu $m CMOS process available from MOSIS at 25 $^{\circ}$C with $\pm $0.8 V supply voltage. Through the use of resistive compensation with different passive resistance values, the voltage mode responses present $\pm $0.25 V dynamic range with THD less than 0.114% and wide bandwidth extended from 3.42 GHz to 4.1 GHz. The current mode responses show $\pm $150 $\mu $A dynamic range with a maximum THD value about 0.083% and large bandwidth expanded from 2.67 GHz to 3.12 GHz.

Design and Analysis of Tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) with Enhanced Performance and Its Application in Filters

This paper proposes a high performance tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) where transconductance of VDIBA is enhanced by using programmable positive feedback technique and bandwidth is enhanced by using resistive compensation technique. The enhanced performance of proposed VDIBA is demonstrated by presenting detailed frequency analysis. Furthermore, it is verified that transconductance of proposed VDIBA can be enhanced up to 10.6 mS at tuning current (Ic) of 100 µA. Moreover, resistive compensation technique enhance bandwidth of propose circuit up to 263 MHz. To illustrate the effectiveness of proposed circuit, voltage mode universal biquad filter is designed as an application example. The pole frequency of proposed filter is tunable in range of 10.5---83.4 MHz. The proposed VDIBA and its filter applications are designed and simulated using TSMC 0.18 µm CMOS technology in Cadence virtuoso schematic composer at ± 0.6 V supply voltage.