Resistivity Silicon Substrate Research Articles

Development of High Performance C-Rich a-SiC Semiconductors with Narrow-Optical Gap By Control of Its Phase Structure

1. Introduction For the expansion of application fields (ex. tailor-made photocatalysts and high-efficiency laser) of semiconductor, novel semiconductor materials with variable optical gaps in the range from 1.2 to 3.0 eV is necessary to be developed. The promising candidate of these semiconductor is carbon-rich amorphous silicon-carbon alloy (C-rich a-SiC).[1] The optical gaps (Eog) of C-rich a-SiC can be changed from 1.2 to 2.7 eV by changing the Si/C ratio. Hetero-junction solar cell comprising N-doped C-rich a-SiC with Eog = 2.7 eV and p-type Si have been reported to show the function of photon to electron conversion.[2] However, solar cells comprising N-doped C-rich a-SiC with Eog from 1.2 to 1.7 eV showed extremely lower conversion efficiencies. Therefore, all of these C-rich a-SiC with Eog from 1.2 to 2.7 eV may not be applied to photoelectronic devices. The objective of this study is to realize C-rich a-SiC with lower Eog (frim 1.2 to 1.7 eV) that have higher semiconductor property and are able to be applied to photoelectronic devices. a-SiC has a multiphase structure in which amorphous Si-C network (Si:C = x:1-x), sp2-hybridized carbon cluster (sp 2 clusters), and silicon-like clusters (Si-cluster) coexist. It has been reported that excess sp2 cluster worked as a recombination center of photoexcited carries. It results in the degradation of efficiencies of photon to electron conversion. In order to realize C-rich a-SiC with lower Eog and higher photon to electron conversion efficiency, the synthesis method that can enhance of ratio of C/Si in amorphous Si-C network and suppress the formation of sp 2 clusters in C-rich a-SiC is necessary to be developed. In this study, CVD synthesis using high-frequency and lower power r. f. plasma was tried to be adopted to induce two types of structural change at C-rich a-SiC. High-frequency and lower power r. f. plasma can avoid the formation of sp 2 clusters in C-rich a-SiC. It results in the semiconductor materials with lower Eog and higher photon to electron conversion efficiency.2. Experimental Nitrogen-doped C-rich a-SiC thin films were synthesized by radio frequency plasma enhanced chemical vapor deposition system (RF-PeCVD) (13.56 MHz, SAMCO Co., Ltd. Model BPD-1) using tetramethylsilane, 1,1,3,3-tetrametyldisilazane and n-hexanes as source materials. C-rich a-SiC thin films were deposited on glass plate and boron-doped silicon (100) substrate (resistivity of 2 W cm) after an in-situ sputter cleaning with argon ions. Substrate temperature was kept at 160 degree C during CVD deposition. The frequency of r.f. power supply was set at 60 MHz and r.f power were changed from 5 to 26 W. The deposition time was 80 minutes. Transmission spectra of N-doped C-rich a-SiC deposited on glass substrates were examined by UV-Vis spectrophotometer (JASCO Co., Ltd. V-670). The performance of heterojunction solar cells was investigated by current-voltage (I-V) measurement (KEYSIGHT, B2901A) with simulated AM 1.5 sunlight (ASAHI SPECTRA, HAL-320). 3. Results and Discussion Eog estimated from transmission spectra (Fig. 1) of resulting N-doped C-rich a-SiC were found to be in the range from 1.40 to 2.96 eV, as shown in Table 1. Eog was able to be controlled to lower value (1.4 eV) thorough the change of the S/C ratios in C-rich a-SiC (by changing the volume ratio of n-hexane in source materials). All hetero-junction solar cells comprising N-doped C-rich a-SiC with various Eog and p-type Si crystal were confirmed to show the function of photon-to electron conversion (Table 1). The improvement of function of photon to electron conversion at C-rich a-SiC with lower Eog (ca. 1.4 eV) might be caused by the suppression of the recombination of photo-exited electrons and holes. In Figure 1, the absorption peak of sp 2 clusters was observed at 1.1 eV and was clearly separated from the absorption peak of amorphous Si-C network (observed at 2.6 eV). The intensity decrease and peak shift to lower energy side of the absorption of sp 2 clusters in Fig. 1 indicates the decrease of the amount of sp 2 clusters and the enlargement of size of sp 2 clusters. These structural change might cause the suppression of recombination of photo-carriers. The relation between Eog and open circuit voltage of solar cell was consistent with estimated value from electronic structure of C-rich a-SiC. It was summarized that the development of C-rich a-SiC semiconductors with lower Eog (in the range from 1.4 to 1.7 eV) that are able to be applied to photo-electronic devices was successfully achieved. 4.

Effect of Silicon Wafer Resistivity on Morphology and Wettability of Silicon Nanowires Arrays

Herein, we prepare vertical and single crystalline silicon nanowires (SiNWs) via a one-step metal-assisted chemical etching method in aqueous NH4HF2/AgNO3 solution. The effects of silicon substrate resistivity and concentrations of NH4HF2 and AgNO3 on the etching process were examined. Two properties were studied, the morphology and the wettability of etched layers. The morphology of the silicon nanowire (SiNW) layers was investigated by scanning electron microscopy (SEM) while the wettability was studied by contact angle measurement system. It was established that the morphology is strongly influenced by etching parameters and their wettability changes from superhydrophilic to hydrophobic.

A modelling and simulation approach for radio frequency (RF) parasitic effects reduction in wafer-level packaging (WLP) of RF-MEMS passive components

RF-MEMS, i.e. micro electro mechanical-systems (MEMS) for radio frequency (RF) passive components, started to make their way into mass-market applications in the telecommunication segment. One critical aspect to ensure easy employment of such devices within systems and sub-systems is that of packaging and encapsulation. In packaging of RF-MEMS, next to the protection of the fragile movable structures and membranes, optimisation of the package electrical performance plays a very important role. In this work, a wafer-level packaging process is investigated and optimised in order to minimise its electrical parasitic effects. The capping silicon substrate resistivity, the substrate thickness and the geometry of through-silicon vias are optimised relying on finite element method electromagnetic simulations. Moreover, a preliminary analysis on the electromagnetic effects of the wafer-to-wafer bonding techniques (i.e. solder bump reflow and Isotropic or anisotropic conductive adhesive – ICA/ACA) is presented.

Impact of doping and silicon substrate resistivity on the blistering of atomic-layer-deposited aluminium oxide

Aluminium oxide (Al2O3) thin films grown at low temperatures using atomic layer deposition (ALD) are known to often suffer from local delamination sites, referred to as “blisters”, after post-deposition annealing during device processing. In this work, we report our observation that doping of the silicon substrate has an effect on blister formation. The introduction of a highly doped layer by diffusion or implantation is found to significantly reduce blistering, compared to the non-doped regions in the immediate vicinity. Similar behavior is observed for both phosphorus and boron doping. Further investigation of this phenomenon using substrates with different resistivities reveals that even when introduced already during silicon crystal growth, doping affects the blistering of aluminium oxide films. Changes in several properties of silicon affected by doping, most importantly surface terminating groups, native oxide growth, and passivation of defects with hydrogen, are discussed as potential reasons behind the observed effect on blistering.

Study the Effect of Different Silicon Substrate Resistivities on the Photoluminescence Results

The silicon-based electroluminescent devices are most commonly used in recent years, especially in optical equipment. The physical properties of the photoluminescence are investigated experimentally in this paper. The silicon substrate resistivity is tested the dependence of the photoluminescence of porous. The formation current density of p-type and highly doped p-type silicon are studied. It is found that using 40 mA/cm2 as a formation current density produced a large number of contributing nanocrystals. The applied low current caused a weak photoluminescence intensity, and the increasing of the formation current density led to increasing the contributing nano crystallizes. For the optimum case with smaller nanocrystallite sizes, the photoluminescence intensity decreased by the fast etching process, and the high current density produced a small number of nanocrystalline sizes and very weak photoluminescence. The higher resistivity doesn’t give a higher intensity and better results in photoluminesces of used porous silicon.

Study on the impact of Fe3O4@Au magnetic nanoparticles in metal-assisted chemical etching

Metal-assisted chemical etch (MACE) has received more and more attention due to its low cost and simple process. Ag, Au, Pt and other noble metals can be used as catalyst in the MACE of silicon. In this paper, MACE on silicon in a hydrofluoric acid (HF) and hydrogen peroxide (H2O2) mixture with different HF-to-H2O2 molar ratio R (R = [HF]/([HF] + [H2O2])) with Fe3O4@Au core–shell magnetic nanoparticles (MNPs) as catalyst under an external magnetic field was investigated. Boron doped p-type (100) silicon wafers with resistivity of 20∼30 Ω · cm and 0.01∼0.03 Ω · cm were used as substrates, respectively. We observed that an average etching rate of 5.17 μm min−1 under an applied magnetic field while the average etching rate was 4 μm min−1 without magnetic field. The factors were investigated that affect the average etched depth in silicon substrate under magnetic field by using MACE. The relationship between the average etching depth and etching time, resistivity of silicon substrate, ratio R, and the concentration of Fe3O4@Au magnetic nanoparticles was also studied. This result can be applied to increase the etching rate of silicon to fabricate a variety of devices, where high aspect ratio silicon structure is demanded.

Substrate resistivity influence on silicon–germanium phototransistor performance

This Letter presents the impact of silicon substrate resistivity on SiGe phototransistors. SiGe phototransistors were fabricated on the commercially available SiGe/Si bipolar technology. The performances of the phototransistors fabricated based on low- and the high-resistive silicon substrate are compared. The phototransistor based on low-resistivity (LR) silicon substrate provides a responsivity of more than double compared to the phototransistor based on a high-resistivity silicon substrate that is fabricated by using the same bipolar transistor technology. The phototransistor fabricated on LR substrate exhibits low-frequency responsivity up to 1.35 A/W (at 50 MHz).

Fabrication and characterisation of RF MEMS capacitive switches tuned for X and Ku bands

Microelectromechanical systems (MEMS) capacitive switches discussed in this paper employ electrostatic actuation to perform switching. Capacitive switches employ inductive tuning for excellent switching characteristics in X and Ku bands. Employing inductive tuning is found to increase the switch beam inductance by a few tens of pico-henry. This enhances the Q factor and enables tuning of isolation over a narrow band of frequencies. Beam inductance can be extracted from the simulated isolation characteristics of the switch by curve fitting. This paper presents design, fabrication and characterisation of inductive tuned MEMS capacitive switches tuned for X and Ku bands. The devices are fabricated on high resistive (10 KΩ) silicon substrate by a five mask process. The characterisation of the fabricated devices are conducted using Cascade probe station and high frequency Power network analyser. Characterisation results show an actuation voltage of 18.5 volts. The insertion - loss and isolation are better than 0.5 dB and -40 dB respectively in the 8-18 GHz band.

Impact of the silicon substrate resistivity and growth condition on the deep levels in Ni-Au/AlN/Si MIS Capacitors

Deep levels formed under different growth conditions of a 200 nm AlN buffer layer on B-doped Czochralski Si(111) substrates with different resistivity were investigated by deep-level transient spectroscopy (DLTS) on metal-insulator-semiconductor capacitors. Growth-temperature-dependent Al diffusion in the Si substrate was derived from the free carrier density obtained by capacitance-voltage measurement on samples grown on p− substrates. The DLTS spectra revealed a high concentration of point and extended defects in the p− and p+ silicon substrates, respectively. This indicated a difference in the electrically active defects in the silicon substrate close to the AlN/Si interface, depending on the B doping concentration.

Static and Dynamic Magnetization Investigation in Permalloy Electrodeposited onto High Resistive N-Type Silicon Substrates

The present study reports on the development of permalloy thin films obtained by electrodeposition onto low-doped n-type silicon substrates. While changing from non-percolated clusters into percolated thin films upon increasing the electrodeposition time, the static and dynamic magnetic properties of the as-obtained structures were investigated. We found the experimental magnetic results to be in very good agreement with the simulations performed by solving the Landau-Lifshitz for the dynamics of the magnetic moment. For short electrodeposition times we found the static and dynamic magnetization behavior of the as-formed nanoclusters evidencing vortex magnetization with random chirality and polarization, which is explained in terms of dipolar interaction minimization. Indeed, it is herein emphasized that recent applications of ferromagnetic materials in silicon-based spintronic devices, such as logic and bipolar magnetic transistors and magnetic memories, have revived the possible utilization of low cost and simple electrodeposition techniques for the development of these upcoming hetero-nanostructured devices.

Study on the impact of silicon doping level on the trench profile using metal-assisted chemical etching

Metal-assisted chemical etching (MACE) has been used as a promising alternative method to fabricate micro/nano-structures on silicon substrates inexpensively. In this paper, profiles of deep trenches on silicon substrates, with different doping levels, fabricated by MACE were studied. A layer of interconnected gold islands was first deposited onto the silicon substrate as catalyst. Electrochemical etching was then performed in a hydrofluoric acid (HF) and hydrogen peroxide (H2O2) mixture solution with different HF-to-H2O2 ratio ρ (ρ = [HF]/([HF] + [H2O2])). Vertical deep trenches were fabricated successfully by using this method. It was observed that even under identical experimental condition, sidewalls with various tilting angles and different morphology could still form on silicon substrates with different resistivity. This possibly because with different resistivity silicon substrate, the gradient of holes in it greatly changed, and so did the final morphology. As a result, the tilting angle of etched trench sidewall can be tuned from 6° to 96° using silicon substrates with different resistivity and etchants with different ρ. By applying the angle-tuning technique revealed in this study, high aspect ratio patterns with vertical sidewalls could be fabricated and three-dimensional complex structures could be designed and realized in the future.

Electrical characteristics of a novel interposer technique using ultra-low-resistivity silicon-pillars with polymer insulation as TSVs

In this paper, a novel silicon interposer technique using silicon pillars with ultra-low-resistivity as the conductor while polymer Benzocyclobutene (BCB) as liner layer is proposed. Fabrication flow of the proposed interposer structure is developed and implemented. Electrical performances, including transmission performance and signal distortion characteristics, are investigated and presented using 3D full wave simulator and SPICE type circuit simulator such as ANSYS’s HFSS software and Agilent’s ADS software, respectively. The impacts of geometric parameters and resistivity of silicon substrate on electrical characterizations are investigated in both frequency domain and time domain. Results show that the proposed interposer has comparable electrical performances such as return loss and insertion loss with conventional Cu-based through-silicon-via (TSV) structure in frequency region from 0.1GHz to 10GHz, despite of slight degradation at low frequency, but it involves a much simpler and more feasible process flow compared with the latter technique.

An AMC Backed Folded Dipole Slot Antenna Based on CMOS Process

A fold dipole slot antenna backed by artificial magnetic conductor (AMC) structure based on a standard 0.18 um CMOS process on chip application is firstly proposed in this paper. Conventional silicon antenna on chip (AoC) suffers from low radiation performance because the most electromagnetic energy is restricted in silicon substrate as surface wave for its high dielectric permittivity. The energy is dissipated as thermal for low resistivity of silicon substrate. AMC constructed by a periodic 6*6 square patch array is adopted as background to improve radiation performance of the proposed folded dipole slot AoC. Gain of the proposed AMC backed AoC is improved about 3.5 dB compared with that of the same AoC without AMC background.

Investigation of the Silicon Substrate With Different Substrate Resistivities for Integrated Filters With Excellent Performance

In this paper, the impact of substrate resistivity on the functional passive components of radio frequency (RF) complementary metal-oxide-semiconductor circuits for system-on-a-chip applications is investigated. This paper carefully extracted the dielectric constant and loss tangent of the silicon substrate with different substrate resistivities by using the aluminum coplanar waveguide. The different dielectric relaxation (cutoff) frequencies as a function of silicon substrate resistivity are compared under different requirements for substrate noise isolation, RF passive device design, and 3-dB-level RF passive device design. It is found that the new dielectric relaxation frequencies of the silicon substrate, which can be used for the implementation of 3-dB-level RF passive device design, are much higher than for the substrate noise isolation. Finally, the integrated millimeter-wave filter example, a low-pass filter with a filter cutoff frequency of fc = 31 GHz, was designed and evaluated directly on the silicon substrates with different resistivities. Experimental results of the fabricated filter showed good agreement with the simulated results and designed concept.

Changes to Charge and Defects in Dielectrics from Ion and Photon Fluences during Plasma Exposure

Based on this, it is our contention that, within the dielectric, beyond the ion penetration depth, photons are responsible for the damage in this region, while on the surface, the damage is primarily caused by ions. Here, the two sources of damage generated during plasma processing will be considered to determine the effects of ion and photon fluences on the damage. They are charge accumulation and defect-state formation. This article establishes the roles of photons and ions in charge accumulation and defect-state formation in dielectric materials. In order to determine this, electron-spin resonance ESR spectroscopy measurements were made to detect the modifications of the interfacial defect states and surface potential measurements with a Kelvin probe were used to detect the charge accumulation. Previously, VUV and UV exposures from synchrotron radiation and HgAr lamp have been shown to be responsible for the interlayer defect-state modifications in the dielectrics. 12 As a test sample, we used atomic-layer-deposited 20-nm-thick HfO2 on 100Si. Note that the dielectric sample is ultrathin which guarantees a modification of the interfacial defects. The resistivity of silicon substrate is 4000 cm which is needed to obtain effective ESR measurements. 13 An electron cyclotron resonance plasma system 9 was utilized to provide the plasma exposure of the dielectric films. Argon plasma was used to minimize the creation of free radicals, 14 so that the ion and photon bombardments were the primary sources of potential damage. To vary the ion and photon fluences, pressure and microwave power were scanned between ranges of 5 and 30 mTorr and 100 and 400 W, respectively. The pressure was varied using a mass-flow controller. For any combination of pressure and power, the ion flux can be calculated using the continuity equation 15 as i = nivi = nisuB 1

65-nm CMOS Monolithically Integrated Subterahertz Transmitter

This letter presents a transmitter for subterahertz radiation (up to 160 GHz), which consists of a nonlinear transmission line (NLTL) and an extremely wideband (EWB) slot antenna on a silicon substrate of low resistivity (10 Ω·cm). The fabrication was realized using a commercially available 65-nm CMOS process. On-wafer characterization of the whole transmitter, of the stand-alone EWB antenna, and of the stand-alone NLTL is presented. Reflection measurements show that the stand-alone EWB antenna has a -10-dB impedance bandwidth in the frequency bands of 75-100 GHz and 220-325 GHz, which agrees very well with the simulation results. The simulated radiation patterns of the antenna are also presented, indicating that the transmitter has an ominidirectional performance. The output power of the NLTL alone and of the transmitter is measured up to 160 GHz, from which the power gain of the on-chip antenna is derived and has a maximum value of -9.5 dBi between 90 and 120 GHz.

Simulation and study of the influence of the buffer intrinsic layer, back-surface field, densities of interface defects, resistivity of p-type silicon substrate and transparent conductive oxide on heterojunction with intrinsic thin-layer (HIT) solar cell

The influence of various parameters such as buffer intrinsic layers, back-surface fields, densities of interface defects ( D it ), the resistivity of p-type silicon substrates ( ρ) and then work function of transparent conductive oxide ( ϕ TCO ) on heterojunction with intrinsic thin-layer (HIT) solar cell performance was investigated using software simulation. Automat for the simulation of heterostructures (AFORS-HET) software was used for that purpose. Our results indicate that band bending, which is determined by the band offsets at the buffer intrinsic/c-Si and/or the c-Si/back-surface field heterointerface, could be critical to solar cell performance. The effect of band bending on solar cell performance and the dependence of cell performance on ρ and ϕ TCO were investigated in detail. Eventually, suggestive design parameters for HIT solar cell fabrication are proposed.

Design and Fabrication of 1.25-Gb/s Full-Triplex Transceiver Module With PLC on a Lossy Si Substrate for G/E-PONs

1.25 Gb/s optoelectronic full-triplex transceiver module with planar-lightwave-circuits was designed and fabricated for the fiber-to-the-home services according to G/E-PONs standards. A low electrical crosstalk of the critical characteristics for the reliable operation of the 1.25 Gb/s full-triplex transceiver module is intensively investigated because the electrical crosstalk on a resistive silicon substrate is more serious than that on a dielectric substrate. It is observed that the performances of the transmitter and receiver satisfy the transmitter and receiver specifications defined in the standards. From this proposed module layout, a design convenience as well as a great reduction of the silicon substrate size by about 50% was completely achieved. Consequently, the 1.25 Gb/s full-triplex transceiver module was fabricated with electrical and mechanical packaging technologies such of a low crosstalk design and a passive alignment method.

Design Considerations for Linear Amplification and Low-Insertion Loss Thin-Film Silicon-on-Insulator Power Metal–Oxide–Semiconductor Field-Effect Transistors

This paper investigate for designing thin-film silicon-on-insulator (SOI) power metal–oxide–semiconductor field-effect transistors (MOSFETs) for linear-amplification and single pole double throw (SPDT)-switch applications. Considering 3.3-V operation (with a lithium ion battery as a power source), channel length of 0.5 µm is the best choice. For linear amplification, it is preferable to suppress the parasitic bipolar effect and reduce the on-resistance. For an SPDT switch, it is preferable to reduce on-resistance and use high-resistivity Si substrate. The effect of the silicon substrate resistivity in radio frequency SOI power MOSFET is found in insertion loss of the SPDT switch.

Loss characteristics of silicon substrate with different resistivities

AbstractIn the design of high‐speed and high frequency IC's, the influence of the substrate on the circuit performance must be considered carefully. This work investigates the loss characteristic of silicon substrate with different resistivities and distinguishes theoretically and experimentally the dielectric losses into the intrinsic loss of silicon (tan δD) and the extrinsic substrate leakage loss (tan δL) caused by the finite conductivity of the substrate. The dielectric relaxation (cut off) frequency as a function of silicon substrate resistivity are calculated as considering the conditions of substrate noise isolation and RF passive device design. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1773–1776, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21786