Reset Transition Research Articles

Filament diffusion model for simulating reset and retention processes in RRAM

Resistive switching memory (RRAM) devices are attracting an increasing interest as a possible future technology for ultra-scaled, high-density nonvolatile/dynamic memory. Although the RRAM concept is promising from the integration and scaling viewpoints, the switching mechanism and its controllability are still under debate. This paper addresses the modeling of reset and retention processes in unipolar resistive-switching memory devices. Reset transition and data loss are described in terms of the dissolution of a conductive filament, which is modeled by thermally-activated diffusion of defects/dopants. Carrier transport, Joule heating and diffusion of oxygen ions/vacancies during the electrical pulse and/or the annealing are modeled within a 3D numerical solver. The model can account for the observed dependence of reset voltage on the width of the applied triangular pulse and on the initial resistance for NiO-based RRAM devices. Retention simulations as a function of annealing temperature also agree with available data. The model provides a first example of device simulation tool for the design and the exploration of scaling and performance of RRAM cells.

Intrinsic constrains on thermally-assisted memristive switching

We derived analytical formulas to estimate the effective thermal resistance of a metallic cylinder subjected to Joule heating, surrounded by an insulator and bounded by two constant temperature planes in order to estimate the temperature of the hottest point of the system. These solutions are especially relevant for modeling unipolar resistive switches (or memristive devices), and they provide insight into the performance tradeoffs for a thermally driven reset transition. In particular, our results indicate that a minimum current of 1 μA is required to successfully reset a unipolar switch, even under the most favorable conditions.

Generating a checking sequence with a minimum number of reset transitions

Given a finite state machine M, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states than M. There has been much interest in the automated generation of a short checking sequence from a finite state machine. However, such sequences can contain reset transitions whose use can adversely affect both the cost of applying the checking sequence and the effectiveness of the checking sequence. Thus, we sometimes want a checking sequence with a minimum number of reset transitions rather than a shortest checking sequence. This paper describes a new algorithm for generating a checking sequence, based on a distinguishing sequence, that minimises the number of reset transitions used.

Modeling of Set/Reset Operations in NiO-Based Resistive-Switching Memory Devices

Resistive-switching memory (RRAM) devices are attracting a considerable interest in view of their back-end integration, fast programming, and high scalability. Prediction of the programming voltages and currents as a function of the operating conditions is an essential task for developing compact and numerical models able to handle a large number (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> - 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> ) of cells within an array. Based on recent experimental findings on the set and reset processes, we have developed physics-based analytical models for the set and reset operations in NiO-based RRAMs. Simulation results obtained by the analytical models were compared with experimental data for variable pulse conditions and were found consistent with data. The set transition is described by a threshold switching process at the broken conductive filament (CF), while the reset transition is viewed as a thermally driven dissolution and/or oxidation of the CF. Set and reset models are finally used for reliability predictions of failure times under constant-voltage stress (read disturb) and elevated-temperature bake (data retention).

Impact of Electrode Materials on Resistive-Switching Memory Programming

This letter addresses the impact of electrode materials on programming characteristics of NiO-based resistive-switching memory devices. The use of noble metals for the electrodes, instead of Si contacts, is shown to result in a lowering of the set/reset voltage. This is ascribed to a different chemical composition of the conductive filament (CF) in the set state for varying electrodes, suggesting that atomic diffusion from the electrodes takes place during the formation of the CF at the set process. The results are interpreted on the basis of numerical simulations of the reset transition, which are compared with experimental data.

Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices

This paper addresses the numerical modeling of reset programming in NiO-based resistive-switching memory. In our model, we simulate electrical conduction and heating in the conductive filament (CF), which controls the resistance of the low resistive (or set) state, accounting for CF thermal-activated dissolution. Employing CF electrical and thermal parameters, which were previously characterized on our NiO-based samples, our calculations are shown to match experimental reset and retention characteristics. Simulations show that reset transition is self-accelerated as a consequence of a positive feedback between the thermal dissolution of the CF and local Joule heating in the CF bottleneck, which can account for the abrupt resistance transition in experimental data. Finally, the model is used to investigate the reduction of the reset current, which is needed for device application.

SET to RESET Programming in Phase Change Memories

Experimental data on details of SET (crystalline) to RESET (amorphous) transition are presented for Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Te <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> (GST) nonvolatile memory cell. It is shown that the main source of heat for a SET to RESET transition is the GST bulk and interface regions instead of the contacting electrode. A small-contact-area electrode is used primarily to supply current into and minimize heat loss from the chalcogenide. Increasing bottom contact resistivity offers a scaling path for RESET current with no electrical penalties

A robust control strategy for combining DCV control with economizer control

Combining demand controlled ventilation (DCV) control and economizer control achieves acceptable and even better indoor air quality with minimum coil energy consumption. The control instability during the transition processes between different control modes are among the major difficulties faced when utilizing economizer control and when combining DCV control with economizer control in applications. A robust control strategy, using “freezing”, gain scheduling, integral term reset and feedback transition control for different transition processes, is developed for addressing these problems. They are evaluated on an air handling unit (AHU) using various simulation tests. The test results demonstrate that the robust control strategy allows stable and robust AHU control.