Reset Noise Research Articles

Two ramp reference voltages CDS scheme applied to low noise and high dynamic range PWM pixel

To achieve noise elimination and dynamic range extension in pulse width modulation (PWM) pixels, this paper proposes the new correlated double sampling (CDS) scheme. The proposed CDS scheme uses two ramp reference voltages instead of one two-stage ramp reference voltage. Two reference voltages are both ramp voltages to detect low illumination. Compared to traditional CDS that uses one two-stage ramp reference voltage, proposed CDS guarantees two crosses between photodiode voltage and reference voltages in high illumination. The simulation shows that the maximum photocurrent with proposed CDS is always larger than 10 nA while the maximum photocurrent with traditional CDS is always less than 495 pA at an exposure time of 1 ms and an 8-bit counter. For the PWM pixel adopting proposed CDS, offset of the comparator after CDS operation is 980.479 μV which is reduced by 93.8%, and reset noise of the reset transistor after CDS operation is 11.963 μV which is reduced by 97.1%.

Reset noise reduction method in 3-T pixels

A reset noise reduction method using a feedback amplifier that results in an 80% noise reduction in 3-transistor (3-T) pixels is presented. 3-T pixels are useful for non-visible imaging applications because they have fewer post-processing issues than 4-T pixels and do not require charge transfer. They suffer from reset noise because correlated-double sampling cannot be realized without additional memory. Analysis of the experimental power spectral density indicates potential for further noise cancellation in future devices.

Reset Noise Sampling Feedforward Technique (RNSF) for Low Noise MEMS Capacitive Accelerometer

The reset noise sampling feedforward (RNSF) technique is proposed in this paper to reduce the noise floor of the readout circuit for micro-electromechanically systems (MEMS) capacitive accelerometer. Because of the technology-imposed size restriction on the sensing element, the sensing capacitance and the capacitance variation are reduced to the femto-farad level. As a result, the reset noise from the parasitic capacitance, which is pico-farad level, becomes significant. In this work, the RNSF technique focuses on the suppression of the parasitic-capacitance-induced noise, thereby improving the noise performance of MEMS capacitive accelerometer. The simulation results show that the RNSF technique effectively suppresses the thermal noise from the parasitic capacitance. Compared with the traditional readout circuit, the noise floor of the readout circuit with the RNSF technique is reduced by 9 dBV. The presented circuit based on the RNSF technique is fabricated by a commercial 0.18-μm BCD process and tested with a femto-farad MEMS capacitive accelerometer. The physical measurement results show that, compared with the readout circuit without the RNSF technique, the RNSF technique reduces the noise floor of the readout circuit for MEMS capacitive accelerometer from −72 dBV to −80 dBV. Compared with other similar works, the proposed readout circuit achieves better FoM (FoM=(power×noise floor)/system bandwidth=490 μW·μg/Hz) among the switched-capacitor readout circuits.

Multi-frame super-resolution reconstruction based on mixed Poisson–Gaussian noise

In this paper, a non-blind multi-frame super-resolution (SR) model based on mixed Poisson–Gaussian noise (MPGSR) is proposed. Poisson noise arises from the stochastic nature of the photon-counting process. Readout noise and reset noise inherent to the readout circuitry can be modeled by an additive Gaussian noise. Therefore, a mixed Poisson–Gaussian noise model is more appropriate for real imaging system. Instead of deriving the data fidelity term from the perspective of error norms and the corresponding influence functions, we address the multi-frame SR problem based on a statistical noise model. The derived objective function is decomposed into sub-functions and solved by the alternating direction method of multipliers (ADMM) algorithm which allows using techniques of constrained optimization. The validation of the proposed MPGSR was performed quantitatively and qualitatively on natural and X-ray images. In comparison to the optimization-based and learning-based state-of-the-art methods, we have demonstrated the feasibility of MPGSR and the significance of applying a more appropriate noise model on the SR image reconstruction.

Low-light-level CMOS imaging sensor with CTIA and digital correlated double sampling

This paper presents two low-light-level CMOS image sensors with capacitive transimpedance amplifier (CTIA) and digital correlated double sampling (CDS). In order to achieve high sensitivity for low-light-level CMOS image sensor, the CTIA pixel circuit with a small integration capacitor is used. In order to remove the noise of the low-light-level CMOS image sensor, a digital CDS is designed, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise, pixel fixed-pattern noise (FPN) and the column FPN can be greatly reduced by this digital CDS. Two test chips based on this method with 256 × 256 pixel array are fabricated in a 0.35 μm CMOS technology, one is based on DC-coupled CTIA pixel circuit, and the other one is based on AC-coupled CTIA pixel circuit. These two chips are designed with the same column sigma-delta analog-to-digital (∑∆ ADC), whose resolution is 15-bit. At a frame rate of 7 fps, the low-light-level CMOS image sensor with DC-coupled CTIA pixel circuit and digital CDS can capture recognizable images with the illumination down to 0.05 lux. The low-light-level CMOS image sensor with AC-coupled CTIA pixel circuit can reduce the dark current by reducing the reverse bias voltage of the photodiode.

Automatic selection of correlated double sampling timing parameters

Correlated double sampling (CDS) is a process used in many charge-coupled device readout systems to cancel the reset noise component that would otherwise dominate. CDS processing typically consists of subtracting the integrated video signal during a “signal” period from that during a “reset” period. The response of this processing depends, therefore, on the shape of the video signal with respect to the integration bounds. In particular, the amount of noise appearing in the final image and the linearity of the pixel value with signal charge are affected by the choice of the CDS timing intervals. We use a digital CDS readout system which highly oversamples the video signal (as compared with the pixel rate) to reconstruct pixel values for different CDS timings using identical raw video signal data. We use this technique to develop insights into optimal strategy for selecting CDS timings both in the digital case (where the raw video signal may be available) and in the general case (where it is not). In particular, we show that the linearity of the CDS operation allows subtraction of the raw video signals of pixels in bias images from those in illuminated images to directly show the effects of CDS processing on the final (subtracted) pixel values.

High-DR CMOS Fluorescence Biosensor With Extended Counting ADC and Noise Cancellation

Accurately resolving small fluorescence power variations in presence of noise and high-background tissue autofluorescence from deep brain structures with a fiber photometry system requires highly linear and sensitive photo detectors. This paper presents a high-dynamic range (DR) CMOS biosensor fusing a low-noise photosensing front-end with a high-precision extended counting analog-to-digital converter (ADC) with noise cancellation to detect florescence neural signal fluctuations of very low incident power. The 7 MSBs are resolved by a first order continuous-time resettable $\Sigma \Delta $ ADC, whereas the residue voltage is quantized by a 10-bit single slope ADC for enabling wide-dynamic range and high-precision fluorescence sensing. The reset noise is canceled out by an embedded noise cancellation scheme which is subtracting the reset noise from the signal using a correlated double sampling scheme. Unlike other solutions, the biosensor has a short conversion time of $306.5~\mu \text{s}$ compared to a typical fluoresence sampling period of 10 ms, providing a very low duty cyle of 3%, which is a key to achieve low excitation source power consumption in this application to extend system autonomy, and to avoid photobleaching and phototoxicity in the tissue. The proposed optoelectronic biosensor is implemented in a 0.18- $\mu \text{m}$ CMOS technology, consuming $93~\mu \text{W}$ from a 3.3-V supply voltage while achieving a DR of 104 dB, a minimum detectable current of $1.3~\text {pA}_{\mathrm{ rms}}$ , and a chip area of 0.475 mm2. We present the measured performance of the biosensor using an optical experimental setup including a LED driver, a fiber optic, and a test board.

Memristors for Secret Sharing-Based Lightweight Authentication

User authentication is one of the most fundamental security problems that design effective ways of identifying single or multiple entities using shared information, signatures, or intrinsic properties of the user(s). Password-based authentication is standard in the computer systems; however, passwords usually have low entropy content, and therefore vulnerable to dictionary attacks. Furthermore, password storage and simultaneous multiparty authentication also pose security and privacy concerns. Secret sharing-based techniques during password enrollment are found to be helpful in securing key storage in the authentication server, and in assisting multiparty authentication without exposing individual identity. However, secret sharing techniques, such as Shamir’s secret sharing, are computationally expensive; therefore, its implementation in power-constrained systems is elusive. To address these problems, we have demonstrated how secure and lightweight user authentication techniques can be designed using several well-known properties of memristive devices. For developing our secret sharing-based computationally lightweight user authentication protocols, first, we define essential utility functions, such as Read State, SET Pulse Count, Preconditioning, and so on, for controlling conductive filament formation in memristive devices. Next, we demonstrate the implementation of hardware-dependent simple authentication protocols that can ensure secure key storage using secret sharing protocol derived from Shamir and Naor’s visual cryptographic constructs. Then, we lay out the required hardware design and discuss the potential attacks to these protocols and the corresponding countermeasures. We conclude that, under realistic attacking assumptions, the proposed protocols are secure. Finally, using PTM’s 65-nm MOSFET models and Stanford’s variation-aware memristor models, we perform HSPICE simulation of the secret-reconstruction and authentication units to demonstrate the reliability of the hardware designs against SET–RESET unbalance, noise, temperature fluctuations, and aging.

QLog Solar-Cell Mode Photodiode Logarithmic CMOS Pixel Using Charge Compression and Readout.

In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light conditions and logarithmic response in high light conditions. The charge transfer readout efficiently suppresses the reset (KTC) noise by using true correlated double sampling (CDS) in low light conditions. In high light conditions, thanks to charge domain logarithmic compression, it has been demonstrated that 3000 electrons should be enough to cover a 120 dB dynamic range with a mobile phone camera-like signal-to-noise ratio (SNR) over the whole dynamic range. This low electron count permits the use of ultra-small floating diffusion capacitance (sub-fF) without charge overflow. The resulting large conversion gain permits a single photon detection capability with a wide dynamic range without a complex sensor/system design. A first prototype sensor with 320 × 240 pixels has been implemented to validate this charge domain logarithmic pixel concept and modeling. The first experimental results validate the logarithmic charge compression theory and the low readout noise due to the charge-transfer-based readout.

Design of a Low Noise Active Pixel Sensor using Complementary Metal-Oxide-Semiconductor Technology

In this paper, our focus is on designing of complementary metal-oxide-semiconductor (CMOS) photodiode based active pixel sensor (APS) and performance analysis and achievements for CMOS image sensor. Different important design parameters like photocurrent, conversion gain, conversion factor, dynamic range, readout speed, and quantum efficiency have been calculated. Noise is also considered for the design at different phase of operations of CMOS APS. Various design parameters of our design are computed and compared with simulated results. Noise calculation shows that the pixel noise is dominated by reset noise.

Analysis of Subthreshold Current Reset Noise in Image Sensors.

To discuss the reset noise generated by slow subthreshold currents in image sensors, intuitive and simple analytical forms are derived, in spite of the subthreshold current nonlinearity. These solutions characterize the time evolution of the reset noise during the reset operation. With soft reset, the reset noise tends to when , in full agreement with previously published results. In this equation, is the photodiode (PD) capacitance and m is a constant. The noise has an asymptotic time dependence of , even though the asymptotic time dependence of the average (deterministic) PD voltage is as slow as . The flush reset method is effective because the hard reset part eliminates image lag, and the soft reset part reduces the noise to soft reset level. The feedback reset with reverse taper control method shows both a fast convergence and a good reset noise reduction. When the feedback amplifier gain, A, is larger, even small value of capacitance, , between the input and output of the feedback amplifier will drastically decrease the reset noise. If the feedback is sufficiently fast, the reset noise limit when , becomes in terms of the number of electron in the PD. According to this simple model, if CPD = 10 fF, CP/CPD = 0.01, and A = 2700 are assumed, deep sub-electron rms reset noise is possible.

Low-noise reset technique of an asynchronous charge-pulse-detecting pixel for single-photon X-ray imaging

This paper presents a low-noise reset technique of an asynchronous charge-pulse-detecting pixel for single-photon X-ray imaging. The proposed slow-slope ramp (S2R) reset scheme provides a reset-noise-discharging loop circuit and effectively eliminates the residual noise charge stored on the sampling capacitor by extending the falling transition time of the reset signal. In addition, the presented S2R reset signal generation circuit accurately and effectively controls the optimum switching voltage and the falling transition time of the reset signal. The prototype detector chip was implemented by using a 130-nm complementary metal-oxide semiconductor (CMOS) process. With the quantitative analysis and the measurement results, we were able to verify that the reset noise was reduced exponentially, corresponding to the falling transition time of the reset signal. Based on the chip measurement results, the reset-noise level could be decreased by more than seven-fold by virtue of the proposed reset technique.

Speedster-EXD: a new event-driven hybrid CMOS x-ray detector

The Speedster-EXD is a new 64x64 pixel, 40 $\mu$m pixel pitch, 100 $\mu$m depletion depth hybrid CMOS X-ray detector (HCD) with the capability of reading out only those pixels containing event charge, thus enabling fast effective frame rates. A global charge threshold can be specified, and pixels containing charge above this threshold are flagged and read out. The Speedster detector has also been designed with other advanced in-pixel features to improve performance, including a low-noise, high-gain CTIA amplifier that eliminates interpixel capacitance crosstalk (IPC), and in-pixel Correlated Double Sampling (CDS) subtraction to reduce reset noise. We measure the best energy resolution on the Speedster-EXD detector to be 206 eV (3.5 %) at 5.89 keV and 172 eV (10.0 %) at 1.49 keV. The average IPC to the four adjacent pixels is measured to be 0.25 $\pm$ 0.2 % (i.e. consistent with zero). The pixel-to-pixel gain variation is measured to be 0.80 $\pm$ 0.03 %, and a Monte Carlo simulation is applied to better characterize the contributions to the energy resolution.

On the Mathematical Foundations of Computational Photography

Flutter shutter (coded exposure) cameras allow to extend indefinitely the exposure time for uniform motion blurs. Recently, Tendero et al. (SIAM J Imaging Sci 6(2):813---847, 2013) proved that for a fixed known velocity v the gain of a flutter shutter in terms of root means square error (RMSE) cannot exceeds a 1.1717 factor compared to an optimal snapshot. The aforementioned bound is optimal in the sense that this 1.1717 factor can be attained. However, this disheartening bound is in direct contradiction with the recent results by Cossairt et al. (IEEE Trans Image Process 22(2), 447---458, 2013). Our first goal in this paper is to resolve mathematically this discrepancy. An interesting question was raised by the authors of reference (IEEE Trans Image Process 22(2), 447---458, 2013). They state that the "gain for computational imaging is significant only when the average signal level J is considerably smaller than the read noise variance $$\sigma _r^2$$?r2" (Cossairt et al., IEEE Trans Image Process 22(2), 447---458, 2013, p. 5). In other words, according to Cossairt et al. (IEEE Trans Image Process 22(2), 447---458, 2013) a flutter shutter would be more efficient when used in low light conditions e.g., indoor scenes or at night. Our second goal is to prove that this statement is based on an incomplete camera model and that a complete mathematical model disproves it. To do so we propose a general flutter shutter camera model that includes photonic, thermal (The amplifier noise may also be mentioned as another source of background noise, which can be included w.l.o.g. in the thermal noise) and additive [The additive (sensor readout) noise may contain other components such as reset noise and quantization noise. We include them w.l.o.g. in the readout.] (sensor readout, quantification) noises of finite variances. Our analysis provides exact formulae for the mean square error of the final deconvolved image. It also allows us to confirm that the gain in terms of RMSE of anyflutter shutter camera is bounded from above by 1.1776 when compared to an optimal snapshot. The bound is uniform with respect to the observation conditions and applies for any fixed known velocity. Incidentally, the proposed formalism and its consequences also apply to e.g., the Levin et al. motion-invariant photography (ACM Trans Graphics (TOG), 27(3):71:1---71:9, 2008; Method and apparatus for motion invariant imag- ing, October 1 2009. US Patent 20,090,244,300, 2009) and variant (Cho et al. Motion blur removal with orthogonal parabolic exposures, 2010). In short, we bring mathematical proofs to the effect of contradicting the claims of Cossairt et al. (IEEE Trans Image Process 22(2), 447---458, 2013). Lastly, this paper permits to point out the kind of optimization needed if one wants to turn the flutter shutter into a useful imaging tool.

A New CDS Structure for High Density FPA with Low Power

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

Theory and Measurement of Reset Noise Suppression in CTIA Readout Circuits

The expressions for the reset noise in capacitive-transimpedance-amplifier (CTIA) readout circuits are theoretically derived and confirmed experimentally. The contributions to the reset noise from the thermal current and amplifier noise are considered. The thermal reset noise is found to depend only on the feedback capacitance among the circuit parameters.

A time error model for time-based PWM pixel with correlated double sample in the circumstance of nonlinear response

A time error mathematical model is proposed to study the impact of nonlinear response and noises on imaging of time-based Pulse Width Modulation (PWM) pixel with the Correlated Double Sampling (CDS). The errors introduced by nonlinearity and certain noises, including fixed pattern noise (FPN), reset noise, shot noise and input-referred noise of pixel-level comparator, are studied. The relative error is impacted not only by the noise voltage, but also the comparator reference voltages, Vrefh and Vrefl. In the 0.18μm CMOS process, the simulation result shows that the noises which have the largest impact on imaging are FPN and shot noise. The higher the Vrefh and Vrefl are, the smaller the error is introduced by FPN. The larger the difference between Vrefh and Vrefl is, the better the signal-to-noise ratio (SNR) is. The influence of reference voltage and clock frequency on dynamic range, and the trade-off between dynamic range and speed are also analyzed in this paper. Finally, the rules of reference voltage selection are discussed. The results can serve as a guideline to the design of the time-based PWM pixel with CDS.

Low-power high-accuracy micro-digital sun sensor by means of a CMOS image sensor

A micro-digital sun sensor (μDSS) is a sun detector which senses a satellite’s instant attitude angle with respect to the sun. The core of this sensor is a system-on-chip imaging chip which is referred to as APS+. The APS+ integrates a CMOS active pixel sensor (APS) array of 368×368 pixels , a 12-bit analog-to-digital converter, and digital signal processing circuits. The μDSS is designed particularly for microsatellite applications, thus low power consumption is the major design consideration. The APS+ reduces power consumption mainly with profiling and windowing methods which are facilitated by the specific active-pixel design. A prototype of the APS+ which is designed in a standard 0.18-μm CMOS process is presented. The APS+ consumes 21 mW at 10 fps, which is 10 times less than the state of the art. In order to improve noise performance, a reset noise reduction method, quadruple sampling (QS), is implemented. QS reduces the effect of the reset noise compared to the conventional delta double sampling method, even in a 3-transistor active pixel structure. The APS+ obtains an accuracy of 0.01 deg with the QS method.

A 1500 fps Highly Sensitive 256$\,\times\,$256 CMOS Imaging Sensor With In-Pixel Calibration

High-speed CMOS imaging sensors (CIS) normally have low sensitivity because of the large integration capacitance. They also have high noise because pixel circuits cannot implement correlated double sampling (CDS) to remove the pixel reset noise. For applications, such as micro-computed tomography (micro-CT), this is a major limitation. In this work, we developed a technique to achieve high sensitivity and low noise for high-speed CIS. To maximize the sensitivity, we designed a new capacitive transimpedance amplifier (CTIA) pixel with a tiny metal-oxide-metal capacitor. The pixel circuit also implements CDS. As a result, the temporal noise is greatly reduced, and the sensitivity improves dramatically. To compensate the mismatch of small integration capacitors across the pixel array, an on-chip calibration scheme with in-pixel circuits is developed. Fully differential column circuits are designed to suppress the power supply injection in the large array of high-speed column circuits. A successive-approximation analog-to-digital (SAR ADC) is designed to achieve 10-bit resolution and to fit in the 15-μm column pitch. For testing modes, column circuits are configured into a two-step ADC to provide 13-bit dynamic range. The 256 × 256 CIS design is fabricated in a 0.18-μm CMOS process. The imager samples up to 1500 fps. The pixel integration capacitor is 0.7 fF, which enables 68.5 V/lux · s sensitivity under the white illumination. The CIS temporal noise is 13.6e-. This sensitivity and noise performances are much better than previous high-speed CIS benchmark designs. Running at 1500 fps, the CIS can capture recognizable images with illumination down to 1 lux. The on-chip calibration suppresses the fixed-pattern noise lower than 0.52%. The prototype chip consumes 390 mW of power.

Power-Efficient High-Speed and High-Resolution Capacitive-Sensor Interface for Subnanometer Displacement Measurements

This paper presents a power-efficient capacitive-sensor interface solution for high-speed and high-resolution subnanometer displacement measurement systems. The proposed solution utilizes a zoom-in capacitance-to-voltage converter stage to remove the offset posed by the large nominal sensor capacitance, which would otherwise dominate the dynamic range. The realized zoom-in factor is 100. The designed circuit uses a correlated-double-sampling technique to cancel both the amplifier offset and the reset noise. First, a printed-circuit-board solution was realized to verify the principle of operation and its limitations. Then, an integrated circuit was designed, fabricated, and tested. Measurement results show that the achievable capacitance resolution is better than 30 aF, from a sensor with a nominal capacitance of 10 pF, which translates into a dynamic range of 18 b. The measurement latency is only 5 μs. This performance is achieved with only 2.4-mW power consumption.