A New CDS Structure for High Density FPA with Low Power

Xiao Wang,Zelin Shi

doi:10.1155/2015/767161

Abstract

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

Highlights

Infrared detectors have a wide range of applications in areas of military, research, and manufacture, whose core part is an infrared focal plane assembly
The assembly mainly consists of two parts: focal plane arrays (FPAs) that function to convert radiation to current signal and readout integrated circuits (ROIC) that are responsible for realization of serial read and processing of signals sampled by the FPA
Based on the theory that MOSFETs operating in the subthreshold region consume much less dissipation than those in the depletion region, this paper proposed a low power correlated double sampling (CDS) structure that contains only one sampling capacitor, two switches, and two operation amplifiers (OPs), which saves the layout area [4, 5]

Summary

Introduction

Infrared detectors have a wide range of applications in areas of military, research, and manufacture, whose core part is an infrared focal plane assembly. The assembly mainly consists of two parts: focal plane arrays (FPAs) that function to convert radiation to current signal and readout integrated circuits (ROIC) that are responsible for realization of serial read and processing of signals sampled by the FPA. Applications of focal planes of large format and high density put forward more harsh demand on low power dissipation and small layout area of a ROIC unit cell. Based on the theory that MOSFETs operating in the subthreshold region consume much less dissipation than those in the depletion region, this paper proposed a low power CDS structure that contains only one sampling capacitor, two switches, and two operation amplifiers (OPs), which saves the layout area [4, 5]. The noise calculation model is established, based on which noise analysis has been carried out by the approaches of transfer function and numerical simulation using SIMULINK and Verilog-A, whose results are in good agreement

Circuit Design

Noise Analysis

Simulation Experiment

Conclusion