Memristors for Secret Sharing-Based Lightweight Authentication

Abstract

User authentication is one of the most fundamental security problems that design effective ways of identifying single or multiple entities using shared information, signatures, or intrinsic properties of the user(s). Password-based authentication is standard in the computer systems; however, passwords usually have low entropy content, and therefore vulnerable to dictionary attacks. Furthermore, password storage and simultaneous multiparty authentication also pose security and privacy concerns. Secret sharing-based techniques during password enrollment are found to be helpful in securing key storage in the authentication server, and in assisting multiparty authentication without exposing individual identity. However, secret sharing techniques, such as Shamir’s secret sharing, are computationally expensive; therefore, its implementation in power-constrained systems is elusive. To address these problems, we have demonstrated how secure and lightweight user authentication techniques can be designed using several well-known properties of memristive devices. For developing our secret sharing-based computationally lightweight user authentication protocols, first, we define essential utility functions, such as Read State, SET Pulse Count, Preconditioning, and so on, for controlling conductive filament formation in memristive devices. Next, we demonstrate the implementation of hardware-dependent simple authentication protocols that can ensure secure key storage using secret sharing protocol derived from Shamir and Naor’s visual cryptographic constructs. Then, we lay out the required hardware design and discuss the potential attacks to these protocols and the corresponding countermeasures. We conclude that, under realistic attacking assumptions, the proposed protocols are secure. Finally, using PTM’s 65-nm MOSFET models and Stanford’s variation-aware memristor models, we perform HSPICE simulation of the secret-reconstruction and authentication units to demonstrate the reliability of the hardware designs against SET–RESET unbalance, noise, temperature fluctuations, and aging.