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A GexSe1-x switch-only-memory technology through polarized atomic distribution

Ovonic threshold switching (OTS) materials that are frequently used with a resistor (1S1R) in memory devices have been found to show controllable and reversible memory properties, which could enable new memory architectures. Here, we examine the impact of composition on the polarity-dependent memory properties of GexSe1-x OTS materials and reveal that an increase in Se content results in a higher set voltage threshold (Vth), a lower reset current (IRST), and a higher set energy. Specifically, Ge56Se44 demonstrates two distinct Vth of 5.1 and 3.8 V, which retain after annealing at 85 ℃ for one day. We fabricated Ge56Se44 into 1000 by 1000 cross-point pillar arrays and tested 100 of them. The results demonstrated that these Ge56Se44 devices show similar memory properties with a reset speed of 1 μs, a set speed of 50 ns, and an endurance of over 105 cycles. Interestingly, the Ge56Se44 pillars’ reset and set states could be attributed to polarized atomic distributions. By utilizing GexSe1-x, we demonstrate a true cross-point switch-only-memory technology and provide mechanistic insights for self-selecting OTS materials.

Reduction of write current with improved thermal stability in GeSe2 doped Sb2Te3 films for phase change memory applications

Chalcogenide alloy-based semiconductors have gained significant attention in recent decades due to its applications in phase change memory (PCM). Sb2Te3 has proven to be an alternative to Static and Dynamic Random Access Memory and can be a suitable candidate for commercial memory devices due to their fast switching speed. However, Sb2Te3 suffers from low amorphous phase stability and high RESET current, which needs further improvement for high power efficiency. In this work, we have prepared (Sb2Te3)1−x (GeSe2) x (x = 0.06, 0.12, 0.18, 0.24, 0.3) films to investigate their PCM properties. The films showed a rise in transition temperature to transform from high resistive amorphous (RESET) to low resistive crystalline (SET) states with doping that leads to significant enhancement in amorphous phase stability. For 30% doping of GeSe2 in Sb2Te3, the data retention temperature increases from 20.2 °C to 84.6 °C, and the resistance contrast also increases from 102 to 105. The rise in electrical resistance with doping in the amorphous as well as crystalline states leads to a drop in threshold current (I th) from 3.5 to 0.8 mA. This also reduces the RESET and SET currents. By analyzing the samples using finite element method, it was found out that the high resistance materials produce more heat, resulting in a lower write current in an energy efficient PCM device.

Low reset current mushroom cell phase‐change memory (PCM) using fiber‐textured homostructure GeSbTe on highly oriented seed layer

We report a low reset current 1T1R mushroom cell phase‐change memory (PCM) device that uses fiber‐textured homostructure GeSbTe (GST) grown on highly‐oriented TiTe2 seed layer. The homostructure device outperformed the industry standard device, that uses doped polycrystalline GST, on most figures of merit. The homostructure devices were also benchmarked against superlattice PCM devices with 10 periods of 5/5nm GST/Sb2Te3 grown on the TiTe2 seed layer, and were found to have same low reset current. We also observed by TEM that the alternating layers of GST/Sb2Te3 and TiTe2/Sb2Te3 in superlattice devices is intermixed in the switched region after the devices are cycled with reset/set pulses. Additionally, when the superlattice device is left in the set state the intermixed switched region crystallinity is textured and exhibits van der Waals gaps. The superlattice PCM devices require a precise layered structure that is hard to yield on a full wafer scale. In contrast, fiber‐textured homostructure PCM cells reported here are easily manufacturable, while providing similarly low reset current and low resistance drift which makes this device suitable for analog AI computation.This article is protected by copyright. All rights reserved.

Forming-Free, Low-Voltage, and High-Speed Resistive Switching in Ag/Oxygen-Deficient Vanadium Oxide(VOx)/Pt Device through Two-Step Resistance Change by Ag Filament Formation.

Forming-free, low-voltage, and high-speed resistive switching is demonstrated in an Ag/oxygen-deficient vanadium oxide (VOx)/Pt device via the facilitated formation and rupture of Ag filaments. Direct current (DC) voltage sweep measurements exhibit forming-free switching from a high-resistance state (HRS) to a low-resistance state (LRS), called SET, at an average VSET of +0.23 V. The reverse RESET transition occurs at an average VRESET of -0.07 V with a low RESET current of <1 mA. Reversible switching operations are stable with an HRS/LRS resistance ratio >103 during repeated measurements for thousands of cycles. In pulse measurements, switching occurs within 100 ns at an amplitude of +1.5 V. Notably, a two-step resistance change is observed in the SET operation, where the resistance first partially decreases due to Ag+ ion accumulation in VOx and then further decreases to the LRS after hundreds of nanoseconds upon complete filament formation. The VOx layer deposited to be mostly amorphous with oxygen deficiency from V2O5 has abundant vacancies and expedites Ag+ ion migration, thus realizing forming-free, high-speed, and low-voltage switching. These characteristics of the facilitated Ag filament formation using the substoichiometric VOx layer are highly beneficial for use as stand-alone nonvolatile memory and in-memory computing elements.

Phase-change heterostructure with HfTe2 confinement sublayers for enhanced thermal efficiency and low-power operation through Joule heating localization

Although phase-change random-access memory (PCRAM) is a promising next-generation nonvolatile memory technology, challenges remain in terms of reducing energy consumption. This is primarily because the high thermal conductivities of phase-change materials (PCMs) promote Joule heating dissipation. Repeated phase transitions also induce long-range atomic diffusion, limiting the durability. To address these challenges, phase-change heterostructure (PCH) devices that incorporate confinement sublayers based on transition-metal dichalcogenide materials have been developed. In this study, we engineered a PCH device by integrating HfTe2, which has low thermal conductivity and excellent stability, into the PCM to realize PCRAM with enhanced thermal efficiency and structural stability. HEAT simulations were conducted to validate the superior heat confinement in the programming region of the HfTe2-based PCH device. Moreover, electrical measurements of the device demonstrated its outstanding performance, which was characterized by a low RESET current (∼1.6 mA), stable two-order ON/OFF ratio, and exceptional cycling endurance (∼2 × 107). The structural integrity of the HfTe2 confinement sublayer was confirmed using X-ray photoelectron spectroscopy and transmission electron microscopy. The material properties, including electrical conductivity, cohesive energy, and electronegativity, substantiated these findings. Collectively, these results revealed that the HfTe2-based PCH device can achieve significant improvements in performance and reliability compared with conventional PCRAM devices.

Resistance Drift in Melt-Quenched Ge2Sb2Te5 Phase Change Memory Line Cells at Cryogenic Temperatures

We characterized resistance drift in phase change memory devices in the 80 K to 300 K temperature range by performing measurements on 20 nm thick, ∼70–100 nm wide lateral Ge2Sb2Te5 (GST) line cells. The cells were amorphized using 1.5–2.5 V pulses with ∼50–100 ns duration leading to ∼0.4–1.1 mA peak reset currents resulting in amorphized lengths between ∼50 and 700 nm. Resistance drift coefficients in the amorphized cells are calculated using constant voltage measurements starting as fast as within a second after amorphization and for 1 h duration. Drift coefficients range between ∼0.02 and 0.1 with significant device-to-device variability and variations during the measurement period. At lower temperatures (higher resistance states) some devices show a complex dynamic behavior, with the resistance repeatedly increasing and decreasing significantly over periods in the order of seconds. These results point to charge trapping and de-trapping events as the cause of resistance drift.

Variability in HfO2-based memristors described with a new bidimensional statistical technique.

A new statistical analysis is presented to assess cycle-to-cycle variability in resistive memories. This method employs two-dimensional (2D) distributions of parameters to analyse both set and reset voltages and currents, coupled with a 2D coefficient of variation (CV). This 2D methodology significantly enhances the analysis, providing a more thorough and comprehensive understanding of the data compared to conventional one-dimensional methods. Resistive switching (RS) data from two different technologies based on hafnium oxide are used in the variability study. The 2D CV allows a more compact assessment of technology suitability for applications such as non-volatile memories, neuromorphic computing and random number generation circuits.

Effect of Transition Metal Dichalcogenide Based Confinement Layers on the Performance of Phase-Change Heterostructure Memory.

Phase-change random-access memory is a promising non-volatile memory technology. However repeated phase-change operations can cause durability issues owing to defects formed by long-distance atom diffusion. To mitigate these issues, phase-change heterostructure (PCH) devices with confinement material (CM) layers based on transition metal dichalcogenides (TMDs) such as TiTe2 have been proposed. This study implements PCH devices with additional TMDs, including NiTe2 and MoTe2 , alongside TiTe2 , and analyzes their characteristics by examining the differences in the CM layers. The results show that the NiTe2 -based PCH device demonstrates a RESET current of 1.4mA, 38% lower than that of the TiTe2 -based device, enabling low-power operation. Furthermore, the MoTe2 -based PCH device exhibits a cycling endurance exceeding 107 cycles, a five-fold improvement in durability compare with the TiTe2 -based device. The performance differences observe in each PCH device can be attributed to the variation in the material properties, such as the cohesive energy and electrical conductivity, of the TMDs used as the CM layer. These results provide critical clues to improve the performance and reliability of conventional PCH memory devices.

300 mm integration of a scalable phase change material spacer by inductively coupled plasma etching

To improve the heating efficiency and reduce the reset current of phase change memory, the volume-confined cells have been widely studied by employing highly conformal deposition techniques. In this work, a scalable confined structure with sidewall phase change material spacer is investigated for the integration in 12-inch wafer using physical vapor deposition and the subsequent anisotropic plasma etching back process. The finite element simulations reveal a remarkable 80% increase in heating efficiency by taking the confined structure. The isolated and compact trenches with the aspect ratio ranging from 0.40 to 1.04 are designed to accommodate the sidewall phase change material. The scaling down of the critical dimension of the rail-like spacer is observed as the aspect ratio increases. The spacer width of around 34 nm is well beyond the lithography capability used in this study. These results provide a promising path to fabricate the low-power and high-density memory device in a way fully compatible with the manufacturing technology.

Atomic Layer Deposition of Sb2 Te3 /GeTe Superlattice Film and Its Melt-Quenching-Free Phase-Transition Mechanism for Phase-Change Memory.

Atomic layer deposition (ALD) of Sb2 Te3 /GeTe superlattice (SL) film on planar and vertical sidewall areas containing TiN metal and SiO2 insulator is demonstrated. The peculiar chemical affinity of the ALD precursor to the substrate surface and the 2D nature of the Sb2 Te3 enable the growth of an in situ crystallized SL film with a preferred orientation. The SL film shows a reduced reset current of ≈1/7 of the randomly oriented Ge2 Sb2 Te5 alloy. The reset switching is induced by the transition from the SL to the (111)-oriented face-centered-cubic (FCC) Ge2 Sb2 Te5 alloy and subsequent melt-quenching-free amorphization. The in-plane compressive stress, induced by the SL-to-FCC structural transition, enhances the electromigration of Ge along the [111] direction of FCC structure, which enables such a significant improvement. Set operation switches the amorphous to the (111)-oriented FCC structure.

Innovative Nanocomposites for Low Power Phase‐Change Memory: GeTe/C Multilayers

Innovative nanocomposites consisting of [(GeTe)4 nm/C1 nm]10 multilayers (MLs) deposited by magnetron sputtering are integrated in phase‐change memory (PCM) test devices with a “wall structure.” Scanning transmission electron microscopy (STEM) shows that an ML structure, with crystallized GeTe layers, is kept after integration in as‐fabricated devices and also after an additional annealing of the devices at 425 °C. The programming current (RESET current) required to reach the high resistance state of [(GeTe)4 nm/C1 nm]10 ML devices decreases by 45% after annealing at 425 °C. The reduction in RESET current is 55% and the reduction in drift coefficient is about 40% in ML devices annealed at 425 °C compared to similar devices incorporating Ge2Sb2Te5. STEM imaging, coupled with nano‐beam electron diffraction and electron energy loss spectroscopy, of ML devices in the high resistance state shows that the RESET current reduction after annealing is correlated to a reduction of the amorphized volume.

Cryogenic operation of NanoBridge at 4 K for controlling qubit

A nonvolatile resistive switching of NanoBridgeTM (NB) at 4 K has been demonstrated for realizing the Quantum-classical interface (QCI), in which the challenging of reset operation at cryogenic temperature is successfully achieved. The set voltage of the NB is increased with decreasing temperature, saturated around 150 K and to be 2.55 V at 4 K. The on-state resistances tuned at 1 k–5 kΩ show small temperature dependence down to 4 K due to high residual resistivity. The increased reset current of the NB at 4 K is compensated by the process optimization with thermal engineering and the increased I dsat of the select transistor at 4 K, resulting in stable switching. The low-power QCI featuring NBs is a strong candidate for controlling a large number of qubits at cryogenic temperature.

Optoelectronic Modulation of Interfacial Defects in Lead‐Free Perovskite Films for Resistive Switching

AbstractMultifunctional nonvolatile photoelectronic memory devices with multilevel storage and logic operation are expected to perform logic‐in‐memory computing tasks and overcome the von Neumann bottleneck. Multifunctional resistive random‐access memory (RRAM) devices that are environmentally friendly, durable, and low power consuming are promising candidates for commercial applications. In this work, low‐dimensional, lead‐free perovskite Cs3Bi2Br9 films with high weatherability are used to construct Ag/Cs3Bi2Br9/ITO RRAM devices with multilevel storage and logic operation functions. The devices demonstrate stable resistive switching (RS) up to 3200 cycles, an ultralow reset current (&lt;0.4 mA), self‐compliance, and negative photoconductivity (NPC). Based on their NPC, the Cs3Bi2Br9 RRAM devices are capable of photoelectronic multilevel storage and “OR” logic operations when programmed photoelectronic inputs are given. The interface effect based on the electron detrapping/retrapping processes of Ag/Cs3Bi2Br9/ITO structure is the mechanism proposed for the RS behavior. This work provides new insights regarding the RS behavior of lead‐free perovskite RRAM devices by photoelectronic modulation and highlights the potential of lead‐free perovskite RRAM devices for stable multilevel storage and logic‐in‐memory computing functions.

A Large-Size HfO2 Based RRAM Structure Suitable for Integration of One RRAM with One InGaZnO Thin Film Transistor for Large-Area Applications

This work aims at finding a HfO2-based resistive random-access memory (RRAM) structure suitable for the integration of one RRAM with one InGaZnO thin film transistor (TFT) for large-area applications such as flexible electronic circuits. One of the major concerns is that the compliance current (CC) required for the formation of stable and strong conductive filaments in the forming and set processes as well as the maximum current required in the reset process in a large-size RRAM should be lower than that of the maximum current a TFT can deliver. In this work, an ultrathin Al2O3 layer of 2 nm was inserted between the HfO2 switching layer and the reactive Ti layer of the top electrode in the RRAM with the structure of Pt (bottom electrode)/HfO2/Al2O3/Ti/TiN (top electrode). With the ultrathin Al2O3 layer, the forming voltage was greatly reduced, and the CC for stable forming and set operations and maximum reset current can reach a low current level that an InGaZnO TFT is able to provide, while the device-to-device variation of the forming operation and cycle-to-cycle resistance variations of the set and reset operations are improved significantly.

Conductive Path Mechanism for Bipolar Resistive Switching Characteristics in Lead‐Free Perovskite CsSnBr3‐Based Nonvolatile Memories

Halide perovskites are intensely studied due to their potential excellent properties in electronic devices. However, the toxicity of lead remains as an obstacle on their way toward large‐scale applications. Herein, the lead‐free all‐inorganic perovskite CsSnBr3 film is used as the switching layer to construct nonvolatile resistive switching (RS) memories and the underlying switching mechanism is systematically explicated. Both memories with Ag/CsSnBr3/Pt and Pt/CsSnBr3/Pt structures exhibit reproducible bipolar RS characteristics, including the large on/off ratios and low reset currents. The RS characteristics are attributed to the formation/rupture of nano‐cone‐shaped conductive paths under external voltage bias. In addition, compared with Pt/CsSnBr3/Pt device, the Ag/CsSnBr3/Pt device manifests lower operation set/reset voltages, revealing the formation of higher density or stronger conductive paths. This work might pave the way for the lead‐free all‐inorganic perovskite‐based RS memory devices in high performance emerging commercial applications.

Irregular Resistive Switching Behaviors of Al2O3-Based Resistor with Cu Electrode

In this work, we examined the irregular resistive switching behaviors of a complementary metal–oxide–semiconductor (CMOS)-compatible Cu/Al2O3/Si resistor device. X-ray photoelectron spectroscopy (XPS) analysis confirmed the chemical and material compositions of a Al2O3 thin film layer and Si substrate. Bipolar resistive switching occurred in a more stable manner than the unipolar resistive switching in the device did. Five cells were verified over 50 endurance cycles in terms of bipolar resistive switching, and a good retention was confirmed for 10,000 s in the high-resistance state (HRS) and the low-resistance state (LRS). Both high reset current (~10 mA) and low reset current (&lt;100 μA) coexisted in the bipolar resistive switching. We investigated nonideal resistive switching behaviors such as negative-set and current overshoot, which could lead to resistive switching failure.

Improvement of Phase‐Change Memory Performance by Means of GeTe/Sb2Te3 Superlattices

GeTe/Sb2Te3 superlattices (SLs) obtained by sputtering are integrated in phase‐change memory (PCM) devices with a “wall structure”. The high structural quality of SLs deposited on TiN or SiNx layers, used as metallic bottom heater and dielectric bottom layer in PCM devices, is established by X‐ray diffraction, for as‐grown SLs and after an annealing corresponding to the maximum thermal budget during the integration process. Scanning transmission electron microscopy (STEM) images of SLs within PCM cells confirm that the SL structure is kept after integration. A robust statistical analysis on a large number of devices demonstrates unambiguously that the RESET current is lower in SL devices than in GeTe reference devices and decreases when the Sb2Te3 layer thickness in the SL increases from 2 to 8 nm. STEM imaging of a PCM cell incorporating an SL demonstrates that switching from the low‐ to the high‐resistance state occurs through a melting–quenching process and is not due to crystal–crystal transition or defect reorganization in the SL, in contrast to what is commonly stated in the literature on interfacial phase‐change memories (iPCMs). The origin of the improved switching performance of SL‐based PCM devices is discussed, linked with the impact of swapped bilayers.

Reduced Operation Current of Oxygen-Doped ZrN Based Resistive Switching Memory Devices Fabricated by the Radio Frequency Sputtering Method

In this work, we report the feasibility of resistive switching (RS) properties of oxygen-doped zirconium nitride (O-doped ZrN) films with platinum (Pt) and platinum silicide (PtSi) bottom electrode (BE), produced by a sputtering method. Compared to O-doped ZrN using Pt BE, when Pt/p-Si was used as BE, the foaming voltage slightly increased, but the operation current was reduced by about two orders. In particular, the average reset current of the O-doped ZrN memory cells was reduced to 50 µA, which can delay deterioration of the element, and reduces power consumption. Therefore, the use of PtSi as the BE of the O-doped ZrN films is considered highly effective in improving reliability through reduction of operating current of the memory cells.

Bilayer Modulation With Dual Vacancy Filaments by Intentionally Oxidized Titanium Oxide for Multilayer-hBN RRAM

In this work, an effective bilayer modulation is achieved for the multilayer hexagonal boron nitride (hBN) resistive random-access memory (RRAM) by an insertion of intentionally oxidized titanium oxide layer. The controllable multiple resistance states can be achieved by setting stop voltage of gradual RESET and compliance current during SET, which is beneficial for multilevel storage and neuromorphic application. The switching uniformity and the endurance of memory window are both improved by the effective bilayer modulation. Through experimental data and ab-initio calculation, both the switching and modulation mechanisms are clarified. The effective modulation can be attributed to the multiple thin conductive filaments with dual vacancies within the bilayer stacks of the multilayer hBN and titanium oxide. A significant formation energy difference between the two kinds of vacancy defects existing in bilayer stacks plays the key role for the filament formation through the fixed paths which benefits the switching uniformity. The findings gained from this work can help promote hBN in RRAM application.

Improved Pulse-Controlled Conductance Adjustment in Trilayer Resistors by Suppressing Current Overshoot.

In this work, we demonstrate the enhanced synaptic behaviors in trilayer dielectrics (HfO2/Si3N4/SiO2) on highly doped n-type silicon substrate. First, the three dielectric layers were subjected to material and chemical analyses and thoroughly investigated via transmission electron microscopy and X-ray photoelectron spectroscopy. The resistive switching and synaptic behaviors were improved by inserting a Si3N4 layer between the HfO2 and SiO2 layers. The electric field within SiO2 was mitigated, thus reducing the current overshoot in the trilayer device. The reset current was considerably reduced in the trilayer device compared to the bilayer device without a Si3N4 layer. Moreover, the nonlinear characteristics in the low-resistance state are helpful for implementing high-density memory. The higher array size in the trilayer device was verified by cross-point array simulation. Finally, the multiple conductance adjustment was demonstrated in the trilayer device by controlling the gradual set and reset switching behavior.