Reliable SRAM Research Articles

Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique

Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique

A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations

To efficiently implement searching and logic functions with the SRAM-based in-memory computing (IMC), we need to perform computations on bitlines (BLs) (called compute access) via multiple wordline (WL) activations. However, this may cause prominent read disturbance when the IMC is implemented with the standard 6 T SRAM. To address this reliability issue, existing solutions adopt either auxiliary assistance circuits or alternative bitcell topologies, but they lead to substantial overheads of the access speed or array density. In this article, we propose a novel 8T compute SRAM (CSRAM) for reliable and high-speed in-memory searching and compound logic-in-memory computations. Our 8T CSRAM features a pair of pMOS access transistors and split-WLs dedicated to the compute access. A thorough circuit-level analysis reveals that the pMOS-based compute access port is essential for significantly mitigating the read disturbance. Moreover, we propose an elevated precharge voltage scheme and a low-skewed inverter-based sensing amplifier to improve the sensing speed. We have validated the proposed 8T CSRAM design in a 16 Kb array with a 28-nm CMOS technology. Compared to the state-of-the-art 8 T CSRAM, results show that our design is not only reliable but also 3.1 times faster, with a maximum operating frequency upping to 2.44 GHz.

A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application

A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application

Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications

In this brief, we proposed, based on the polarity upset mechanism of single-event transient voltage of n-channel metal–oxide–semiconductor (nMOS) transistors, a novel radiation hardened by polar design (RHPD) 12T SRAM cell to enhance the reliability and operation speed for space applications. Simulation results in Semiconductor Manufacturing International Corporation (SMIC) 65-nm CMOS commercial standard process show that the proposed RHPD-12T cell can tolerate all single-node upsets. Meanwhile, compared with We-QUATRO, QUATRO, and dual interlocked storage cell (DICE), the write speed of the proposed cell can be reduced by ~41.8 and ~35.3%, and the static power consumption is reduced by ~41.6 and ~46.3%, respectively. Monte Carlo (MC) simulation has proved that under high frequency and low supply (0.6 V) voltage, RHPD-12T has the minimum write failure probability compared with five other SRAM cells.

Design and Analysis of Gate All Around Tunnel FET based SRAM

Tunnel FETs (TFETs) possess all required characteristics for replacing MOSFET device in circuits with stringent requirements particularly for Internet of Things (IoT) and Biomedical applications. In particular Gate-All-Around (GAA) TFET device configuration exhibits higher ION/IOFF ratio and strong control of the gate terminal over the channel. The main objective of this research work is to explore the prospects of using GAATFET device topology for designing low power and reliable SRAM cell. In this work both n-type and p-type Tunnel FET devices have been designed and simulated using Cogenda Visual TCAD tool. Verilog-A model relying on look up tables that are extracted through device simulations has been designed for performing circuit simulations of 6T and 8T SRAM cell involving these novel devices. Device simulation results show that both NTFET and PTFET devices exhibits excellent ION/IOFF ratio and steep subthreshold slope. NTFET device simulation results show 21.2 mV/decade of subthreshold slope and ION/IOFF ratio of 1013. PTFET device has ON current of the similar order as that of NTFET and has extremely low value of OFF current of less than 1 pA. Circuit simulation results show that by using optimized sizing of transistors in outward NTFET access transistor based 6T SRAM cell leads to reliable and fast read and write operation with acceptable values of noise margin. 6T TFET based SRAM cell achieves leakage power reduction by 77.5% in comparison to leakage power consumed by 8T TFET based SRAM thereby making it a favorable choice for memory design.

Power-up control techniques for reliable SRAM PUF

Power-up control techniques for reliable SRAM PUF

Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis

This paper presents two different topologies of 11T SRAM cells with fully half-select-free robust operation for bit-interleaving implementation. The proposed 11T-1 and 11T-2 cells successfully eliminate Read disturb and Write half-select disturb and also improve the Write-ability by using power-cutoff and write “0”/ “1” only techniques. The 11T-1 and 11T-2 cells achieve $1.83 \times $ and $1.7 \times $ higher write-yield while both achieve approximately $2 \times $ higher read-yield as compared with 6T cell (at ${V}_{DD} = 0.9$ V). The proposed 11T-1 cell also shows 13.6% higher mean Write-margin (WM) compared with existing 11T cell. Both the proposed cells successfully eliminate floating node condition encountered in earlier power cut-off cells during write half-select. Monte-Carlo simulation confirms low-voltage operation without any additional peripheral assist circuits. We also present a comparative analysis of Bias Temperature Instability reliability impacting the SRAM performance in a predictive 32nm high-k metal gate CMOS technology. Under static stress, the Read Static Noise Margin (RSNM) reduces for all cells. However, 11T-1 and 11T-2 cells improve RSNM by 2.7% and 3.3% under relaxed stress of 10/90. Moreover, the proposed 11T-1 (11T-2) cell improves WM by 7.2% (13.2%), reduces write power by 28.0% (20.4%) and leakage power by 85.7% (86.9%), degrades write delay by 38.1% (23.3%) without affecting read delay/power over a period of 108 seconds (approx. 3 years). The 11T-1 (11T-2) cell exhibits 4.8% higher (2% lower) area overhead as compared to earlier 11T cell. Hence, the proposed 11T cells are an excellent choice for reliable SRAM design at nanoscale amidst process variations and transistor aging effect and can also be used in bit-interleaving architecture to achieve multi-cell upset immunity.

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.

Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design

Space applications demand highly stable and reliable SRAM circuits for secure and the uninterrupted operation. In this paper, we propose advanced FinFET and self-refreshing logic-based 12T SRAM cell (WWL12T). The dual- ${k}$ gate insulator and symmetric spacer are used to improve the reliability and performance of the FinFET. The outer side high- ${k}$ insulator reduces the charge trapping to the gate oxide and improves the ON current along with reduced short channel effects. WWL12T uses extra word line for bit interleaving aware design and a feedback circuit for stable space applications. In the read operation, the extra ${P}$ -type transistors are active according to the stored data bits and charge the storing nodes using bit-line voltages. The static noise margin and word line write margin of proposed WWL12T SRAM cell under worst case process variation and single charge trapping improve by 6.4% and 8.4%, respectively compared to existing 12T SRAM.

Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling

This paper presents a half-select free 9T SRAM to facilitate reliable SRAM operation in the near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which results in instable operations in 6T SRAM cell, can be completely eliminated by adopting cross-access selection of row and column word-lines. To minimize the area overhead of the half-select free 9T SRAM cell, a bit-line and access transistors between the adjacent cells are shared using a symmetric shared node that connects two cells. In addition, a selective pre-charge scheme considering the preferably isolated unselected cells has also been proposed to reduce the dynamic power consumption. The simulation results with the most probable failure point method show that the proposed 9T SRAM cell has a minimum operating voltage (VMIN) of 0.45 V among the half-select free SRAM cells. The test chip with 65-nm CMOS technology shows that the proposed 9T SRAM is fully operated at 0.35 V and 25 °C condition. Under the supply voltages between 0.35 and 1.1 V, the 4-kb SRAM macro is operated between 640 kHz and 560 MHz, respectively. The proposed 9T SRAM shows the best voltage scalability without any assist circuit while maintaining small macro area and fast operation frequency.

A Novel circuit of SRAM Cell Against Single-Event Multiple Effects for 45nm Technology

As CMOS technology down sized into double digit nanometer ranges, variations are a serious concern due to uncertainty in devices and interconnect characteristics. The single event upset (SEU) is changing the state of a memory cell due to the strike of an energetic particle. The single event multiple effects are likely to increase in nanometer CMOS technology due to reduced device size and scaling of power supply voltage.SRAM cells are sensitive to radiation induced hazards. Therefore, designing a reliable novel SRAM cell is an important challenge against SEU. In this paper, the proposed SRAM cell that provides a better features than their recent proposed SRAM cells. The simulation results and analysis represent that the proposed SRAM cell exhibits the high robustness against single event multiple effects (SEMEs). Moreover, the proposed SRAM cell successfully reduced the power consumption by 41% and write delay by 2% in comparison with the existing radiation-hardened SRAM cells at the cost of circuit complexity. The process corner analysis displays the comparison of power and delay of the proposed and existing SRAM cells. It shows that the proposed memory cell consumes less power than previous memory cells.

A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design

This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the dynamic power consumption at ISO minimum operating voltage $({V}_{\mathrm{MIN}})$ condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit.

Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies

As technology size scales down toward lower two-digit nanometer dimensions, sensitivity of CMOS circuits to radiation effects increases. Static random access memory cells (SRAMs) that are mostly employed as high-performance and high-density memory cells are prone to radiation-induced single-event upsets. Therefore, designing reliable SRAM cells has always been a serious challenge. In this paper, we propose two novel SRAM cells, namely, RHD11 and RHD13, that provide more attractive features than their latest proposed counterparts. Simulation results show that our proposed SRAM cells as compared with some state-of-the-art designs have considerably higher robustness against single-event multiple effects. Moreover, they offer a sensible area overhead advantage so that our proposed RHD11 SRAM cell has 19.9% smaller area than the prominent dual-interlocked cell. The simulation results and analyses show that our proposed SRAM cells, particularly the proposed RHD13, have a considerable lower failure probability among the considered recent radiation-hardened SRAM cells.

Low-power reliable SRAM cell for write/read operation

Low-power reliable SRAM cell for write/read operation

Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

This work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20ns) for the operating voltage of 1.0V. The information is backed-up during POWER-DOWN/RESTORE cycle in two bipolar Oxide Resistive RAMs (OxRRAMs). The proposed NV-SRAM is designed with an 8T2R structure using 22nm FDSOI technology and resistive memory devices based on HfO2. The stability and the reliability of the NV-SRAM cell is investigated by taking into account the variability of the transistors. It is shown that high ROFF/RON is necessary to ensure reliable RESTORE operation and high SRAM yield under cell area and power consumption constraints.

Variability aware low leakage reliable SRAM cell design technique

This paper presents a technique for designing a low power SRAM cell. The cell achieves low power dissipation due to its series connected drivers driven by bitlines and read buffers which offer stack effect. The paper investigates the impact of process, voltage, and temperature (PVT) variations on standby leakage and finds appreciable improvement in power dissipation. It also estimates read/write delay, read stability, write-ability, and compares the results with that of standard 6T SRAM cell. The comparative study based on Monte Carlo simulation exhibits appreciable improvement in leakage power dissipation and other design metrics at the expense of 84% area overhead.

Case Study of Reliability-Aware and Low-Power Design

Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.

A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results

This paper presents the architecture of a CMOS static RAM which is tolerant to radiation-induced upsets. It employs transient current sensing circuits to achieve concurrent, event-driven SEU detection and correction. Tests with simulated upsets and preliminary radiation tests showed the detection of all upsets and proved the effectiveness of the approach.