Reliable Physical Unclonable Function Research Articles

Machine learning attacks resistant strong PUF design utilizing response obfuscates challenge with lower hardware overhead

Physical unclonable function (PUF) is a hardware security primitive with significant application potential. However, strong PUF is vulnerable to machine learning attacks based on modeling attacks. Although various resistance techniques have been proposed, strong PUF suffers from deficiencies in its resistance to machine learning attacks, hardware overhead, and reliability. This study proposes a highly reliable and secure lightweight PUF that complicates the original challenge using an internal response. Specifically, the internal response is used to determine the odd/even bit flip or left/right cyclic shift of the original challenge to achieve preliminary obfuscation, and byte substitution that exploits an S-box is performed on the preliminary obfuscated challenge to achieve deep nonlinear obfuscation. Experimental results on a Xilinx Artix-7 FPGA show that the proposed PUF is not only highly resistant to machine learning (ML) attacks but also has a low hardware overhead. An arbiter PUF(APUF), which uses the proposed obfuscated scheme with a 64-bit challenge length, was evaluated by three advanced machine learning algorithms with up to 600,000 challenge–response-pairs (CRPs) in the dataset, and the observed prediction accuracy was less than 56 %. Moreover, the PUF is unique, reliable, and has a significantly lower hardware overhead than other prior anti-attack PUFs.

Highly Reliable and Secure PUF Using Resistive Memory Integrated Into a 28 nm CMOS Process

Owing to the increased demand for secure communication channels and authentication steps, physical unclonable functions (PUFs) are increasingly important for hardware security. In this article, we report a novel PUF architecture and generation scheme that utilizes the inherent program-time variation of resistive random access memory (ReRAM) cells as an entropy source. ReRAM cells are integrated into a standard 28 nm CMOS manufacturing process, and also show robust non-volatile memory operation. We generated a PUF data set larger than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text{8}}$</tex-math> </inline-formula> bits and verified its randomness using a standard NIST test suite. Further verifications such as inter-and intra-hamming distance, 150 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C data retention of PUF bits, and spatial co-relation tests confirm the high reliability of the generated PUF keys.

Printable Epsilon‐Type Structure Transistor Arrays with Highly Reliable Physical Unclonable Functions (Adv. Mater. 16/2023)

Physical Unclonable Functions In article number 2210621, Bowen Zhu, Hong Wang, and co-workers use printed epsilon-type-structure transistor arrays with a modified indium tin oxide coffee-ring structure to construct physical unclonable functions (PUFs) that demonstrate near-ideal uniformity, uniqueness, randomness, reliability, and low power consumption. Additionally, the PUFs are secure against attack by a powerful machine-learning model without post-processing. The epsilon-type structure provides a printable, simple strategy for high-quality and large-scale hardware secure primitives.

Printable Epsilon-Type Structure Transistor Arrays with Highly Reliable Physical Unclonable Functions.

Printed electronics promises to drive the future data-intensive technologies, with its potential to fabricate novel devices over a large area with low cost on nontraditional substrates. In these emerging technologies, there exists a large digital information flow, which requires secure communication and authentication. Physical unclonable functions (PUFs) offer a promising built-in hardware-security system comparable to biometrical data, which can be constructed by device-specific intrinsic variations in the additive manufacturing process of active devices. However, printed PUFs typically exploit the inherent variation in layer thickness and roughness of active devices. The current in devices with enough significant changes to increase the robustness to external environment noise is still a challenge. Here, printable epsilon-type-structure indium tin oxide transistor arrays are demonstrated to construct high-reliability PUFs by modifying the coffee-ring structure. The epsilon-type structure improves the printing scalability, film quality, and device reliability. Furthermore, the print-induced uncertainty along the channel thickness and length can lead to changes in the carrier concentration. Notably, the randomly distributed printing droplets in a small area significantly increase this uncertainty. As a result, the PUFs exhibit near-ideal uniformity, uniqueness, randomness, and reliability. Additionally, the PUFs are resilient against machine-learning-based attacks with a prediction accuracy of only 55% without postprocessing.

Device authentication with FPGA based self correcting Physical Unclonable Function for Internet of Things

The device authentication of IoT nodes is very important since they are mainly deployed in open unsecure environment. Physical Unclonable Function (PUF) is a fingerprint of chip and may be useful to solve the hardware security issues in IoT network. This fingerprint is based on the inevitable physical variations that occur during the manufacturing of the device and is useful for generating cryptographic keys. These variations are random in nature and extracted through Challenges–Response Pairs. However, the responses of the device are subjected to change in the environmental condition such as temperature variations, humidity alteration, aging effect and voltage variations. The paper presents reliable PUF solution using an efficient error correction scheme. The main contribution of the paper is to design a secure and effective self-error correctable PUF for tiny IoT nodes. The systematic Golay code and decoding algorithm are applied with PUF for improvement of the reliability in IoT applications. The hardware implementation of Golay code based error correction along with PUF is performed on FPGA board to validate the proof of concept as reliable hardware security solution. The proposed design has good performance with 45% uniqueness and 97% of reliability using efficient error correction mechanism. The hardware results show that our proposed self correcting PUF based solution would suited for small sensors in various IoT applications.

Spintronic Physical Unclonable Functions Based on Field-Free Spin-Orbit-Torque Switching.

Physical unclonable function(PUFs) utilize inherent random physical variations of solid-state devices and are a core ingredient of hardware security primitives. PUFs promise more robust information security than that provided by the conventional software-based approaches. While silicon- and memristor-based PUFs are advancing, their reliability and scalability require further improvements. These are currently limited by output fluctuations and associated additional peripherals. Here, highly reliable spintronic PUFs that exploit field-free spin-orbit-torque switching in IrMn/CoFeB/Ta/CoFeB structures are demonstrated. It is shown that the stochastic switching polarity of the perpendicular magnetization of the top CoFeB can be achieved by manipulating the exchange bias directions of the bottom IrMn/CoFeB. This serves as an entropy source for the spintronic PUF, which is characterized by high entropy, uniqueness, reconfigurability, and digital output. Furthermore, the device ensures a zero bit-error-rate under repetitive operations and robustness against external magnetic fields, and offers scalable and energy-efficient device implementations.

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-in-Memory (CIM) systems. However, it is challenging to guarantee the hardware security of STT-mCell-based all-spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for the STT-mCell-based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates the All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61%. With ± 20% supply voltage and 5°C to 105°C temperature variations, the All-Spin PUF shows a strong resiliency. In comparison with state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of the All-Spin PUF against emerging modeling attacks is verified as well.

Functional mobile-based two-factor authentication by photonic physical unclonable functions

Given the rapid expansion of the Internet of Things and because of the concerns around counterfeited goods, secure and resilient cryptographic systems are in high demand. Due to the development of digital ecosystems, mobile applications for transactions require fast and reliable methods to generate secure cryptographic keys, such as Physical Unclonable Functions (PUFs). We demonstrate a compact and reliable photonic PUF device able to be applied in mobile-based authentication. A miniaturized, energy-efficient, and low-cost token was forged of flexible luminescent organic–inorganic hybrid materials doped with lanthanides, displaying unique challenge–response pairs (CRPs) for two-factor authentication. Under laser irradiation in the red spectral region, a speckle pattern is attained and accessed through conventional charge-coupled cameras, and under ultraviolet light-emitting diodes, it displays a luminescent pattern accessed through hyperspectral imaging and converted to a random intensity-based pattern, ensuring the two-factor authentication. This methodology features the use of a discrete cosine transform to enable a low-cost and semi-compact encryption system suited for speckle and luminescence-based CRPs. The PUF evaluation and the authentication protocol required the analysis of multiple CRPs from different tokens, establishing an optimal cryptographic key size (128 bits) and an optimal decision threshold level that minimizes the error probability.

STT-MRAM-Based Reliable Weak PUF

In recent years, micro-nano device characteristics like ferroelectrics and resistive switching are being used to build important security primitives such as Physical Unclonable Function (PUF). The micro-nano device-based hardware security primitives, although with higher security, energy efficiency, and integration density, suffer from serious reliability issues caused by process scaling. To mitigate this issue, this paper introduces a reconfigurable weak PUF based on spin-transfer torque magnetoresistive random-access memory (STT-MRAM), which adopts the crossing switches implemented with simple demultiplexes (DEMUXs) to improve the flexibility and reliability. Moreover, two algorithms, <monospace>neighboring bit lines</monospace> and <monospace>top-<inline-formula><tex-math notation="LaTeX">$n$</tex-math><alternatives><mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="hu-ieq1-3095657.gif" xmlns:xlink="http://www.w3.org/1999/xlink"/></alternatives></inline-formula></monospace> , are proposed to enlarge the gap between two parallel reading currents, thus further enhancing the reliability of PUF responses. Experimental results demonstrate that the proposed PUF scheme achieves good uniqueness (50.64 percent), uniformity (50.02 percent), and bit-aliasing ( <inline-formula><tex-math notation="LaTeX">$\approx$</tex-math></inline-formula> 49.80%). Particularly, the proposed method significantly improves the PUF reliability, achieving low bit error rate (BER <inline-formula><tex-math notation="LaTeX">$\leq$</tex-math></inline-formula> 2.13%) within the range of -20 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C to 90 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C.

Reliability Improvement on SRAM Physical Unclonable Function (PUF) Using an 8T Cell in 28 nm FDSOI

An 8T cell is proposed to improve reliability and radiation tolerance of the static random-access memory (SRAM) physical unclonable function (PUF) which is formed by adding two cascode PMOS transistors biased at on-state to standard 6T cell. Two custom SRAM PUFs in the same batch consisting of 6T cells and 8T cells using 28nm FDSOI process were employed to evaluate characteristics with respect of bit error rate (BER) and inter-chip hamming distance (HD) under an increase of Co-60 total ionizing dose, various supply voltage, ramp-up time, and temperature. According to the experimental result, the BER of the proposed SRAM PUF decreased by 2X under various conditions with better radiation tolerance compared with the 6T one. Both kinds of SRAM PUF have similar inter-chip HD closed to 50%, but the proposed prototype has less variation thanks to better reliability. When supply voltage, ramp-up time, and temperature conditions were set to 400 mV, 100 ms, and 25°C respectively, the proposed SRAM PUF can achieve the lowest BER of only 0.72%. Some design tips of reliable and rad-hard SRAM PUF are given as the design guidance.

Low-Power Two-Phase Clocking Adiabatic PUF Circuit

Internet of Things (IoT) has enabled battery-powered devices to transmit sensitive data, while presenting high power consumption and security issues. To address these challenges, adiabatic-based physical unclonable functions (PUFs) offer a promising solution for low-power and secure IoT device applications. In this study, we propose a novel low-power two-phase clocking adiabatic PUF. The proposed adiabatic PUF utilizes a trapezoidal power clock signal with a time-ramped voltage to achieve an improved energy efficiency and reliable start-up PUF behavior. Static CMOS logic is employed to produce stable challenge-response pairs (CRPs) in the adiabatic mode. The pull-down network is designed to control the PUF cell to charge and discharge its output nodes with a constant supply current during secure key generation. The body effect of PMOS transistors, ambient temperatures, and CMOS process variations are investigated to examine the uniqueness and reliability of the proposed work. The proposed adiabatic PUF is simulated using 0.18 µm CMOS process technology with a supply voltage of 1.8 V. The uniqueness and reliability of the proposed adiabatic PUF are 49.82% and 99.47%, respectively. In addition, it requires a start-up power of 0.47 µW and consumes an energy of 15.98 fJ/bit/cycle at the reference temperature of 27 °C.

Multibit-Generating Pulsewidth-Based Memristive-PUF Structure and Circuit Implementation

As Internet of Things (IoT) devices have evolved, physical unclonable functions (PUFs) have become a popular solution for hardware security. In particular, memristor devices are receiving attention as suitable candidates for reliable PUFs because they can be integrated into nano-cross point array circuits with ultra-high efficiency. However, it has been found that typical 1-bit generating PUFs consume too many challenge–response pairs (CRPs) to generate a single response. This issue has to be overcome to construct a strong and reliable PUF with a large number of valid CRPs. We suggest a bank design and quantizing entropy source method for constructing a multibit-generating PUF. In this paper, we propose a new pulsewidth-based memristive PUF (pm-PUF) architecture that incorporates analog memristor devices and a nano-cross point array. We describe the architecture’s circuit implementation and its operating process in detail. We also evaluate the inter and intra performances of the pm-PUF in terms of randomness, diffuseness, uniqueness, and steadiness to show that the proposed pm-PUF will be a promising solution for a high-density hardware security system.

An Ultracompact Switching-Voltage-Based Fully Reconfigurable RRAM PUF With Low Native Instability

In this brief, an ultracompact and highly reliable physical unclonable function (PUF) is presented based on the mainstream resistive random access memory (RRAM) devices. With the entropy originating from the switching voltage between the high-resistance state (HRS) and the low-resistance state (LRS), the proposed RRAM PUF can be generated during the RRAM's standard SET operation, leading to minimized design overhead. In addition, different from the previous implementations where the adopted RRAM PUF cells are dedicated to the “PUF” function, the proposed RRAM PUF is fully reconfigurable between the “PUF” function and the normal memory function. Moreover, the proposed implementation is validated using a standard 0.13-μm CMOS process plus customized postprocessing dedicated to RRAM devices. Featuring a normalized PUF cell area of 108F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the native instability (i.e., unstable bits) is measured to be as low as 0.28% at the normal condition. With the operating temperature varying from -50 °C to 150 °C and the supply voltage varying from 4 to 6 V, the averaged bit error rate (BER) is reported to be as low as 0.06% and 0.095%, respectively.

Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices

Internet of Things (IoT) devices have stringent constraints on power and energy consumption. Adiabatic logic has been proposed as a novel computing platform to design energy-efficient IoT devices. Physically Unclonable Functions (PUFs) is a promising paradigm to solve security concerns such as Integrated Circuit (IC) piracy, IC counterfeiting, and the like. PUFs have shown great promise for generating the secret bits that can be used in the secure systems in an inexpensive way. However, designing a reliable PUF along with energy-efficiency is a big challenge. Therefore, for energy-efficient and reliable PUFs, we are proposing a novel energy-efficient adiabatic logic-based PUF structure. The proposed adiabatic PUF uses energy recovery concept to achieve high energy efficiency and uses the time ramp voltage to exhibit the reliable start-up behavior. The channel length of the transistors play a major role in controlling manufacturing variations. So, in this article, the circuit simulations are performed with 180nm and 45nm Complementary metal-oxide-semiconductor (CMOS) technology in a Cadence Spectre simulator to analyze the impact of channel length variations. The proposed adiabatic PUF has worst-case reliability of 96.84% and 99.6% with temperature variations at 180nm and 45nm CMOS technology, respectively. Further, the proposed adiabatic PUF consumes 1.071fJ/bit-per cycle at 180nm CMOS technology and 0.08fJ/bit-per cycle at 45nm CMOS technology.

A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test

Physically unclonable functions (PUFs) promise to be a critical hardware primitive for billions of Internet of Things (IoT) devices. The arbiter PUF (A-PUF) is one of the most well-known PUF circuits. However, its FPGA implementation has a poor reliability, and error correction codes (ECCs) are usually needed to eliminate the noise in the responses, which incur additional high hardware overhead and require NVM for helper data storage. In this paper, we present a highly reliable arbiter PUF with improved uniqueness using the bit-self-test (BST) strategy. A delay detection circuit is added into a classical arbiter PUF to test the delay deviation that produces each bit of the PUF response in real-time and mark the response as reliable using a reliability flag when the delay deviation is significantly more than a predefined threshold. Then, the robust responses can be used. We implemented the BST-arbiter PUF on a Xilinx Artix 7 FPGA. The test results show that the selected responses achieve outstanding performance where the bit error rate is less than 10−9, the bias is 50.3%, and the uniqueness is 49.1%. Thus, the BST-APUF, which drastically reduced the ECC overhead, can be applied to lightweight cryptography applications.

Design of Robust, High-Entropy Strong PUFs via Weightless Neural Network

Physically unclonable functions (PUFs) have been explored as lightweight hardware primitives for the purpose of realizing robust security via strong authentication or secure key/ID generation. PUF harness manufacturing process variations for the purpose of generating binary keys or binary functions. An ideal strong PUF is a binary function that maps an m-bit input challenge to an uniquen-bit output response, making it attractive for authentication applications. Unfortunately, real strong PUF implementations suffer from reliability issues where the same challenge may produce different responses in the presence of noise. To overcome this problem, strong PUF leverages the availability of exponential number of challenge-response pairs (CRPs). A successful authentication event requires acquiring multiple CRPs and applying a threshold. In contrast, weak PUFs produce limited keys and are required to be highly reliable. Multiple techniques have been developed to achieve the necessary reliability. An additional prerequisite for strong PUFs is resilience against model-building attacks (cloning) by an adversary, who has observed a few CRPs, to prevent successful prediction of future CRPs. In this work, we first illustrate a strong PUF design that re-purposes a weightless neural network (WNN). Second, we showcase the robustness of WNN-based strong PUFs with respect to machine learning attacks, while providing desirable uniqueness and reliability metrics. Finally, we employ an initial entropy source of highly reliable weak PUF bits mapped to weightless neural networks (WNNs) for the purpose of creating a near-ideal strong PUF in terms of reliability. Our results show that it is possible to create highly reliable WNN–based strong PUFs with < 65 % ML accuracy by using as few as 32 initial reliable weak PUF bits.

A Highly Reliable and Unbiased PUF Based on Differential OTP Memory

Physically unclonable functions (PUF) are essential for hardware identity and security for IoT devices. The PUF consists of a multi-bit string that requires unbiased randomness. A one-time programmable memory (OTPM) uses insulator breakdown in metal-insulator-metal device to switch between insulating (“0”) and conducting (“1”) state. An OTPM based PUF produces an unbiased bit-string if exactly median breakdown voltage(VBD) and time are used. The exact application of median VBD is challenging in an integrated circuit as a conventional-voltage supply-tolerance specification is 10%. In this letter, we propose a differential OTPM-based PUF with a parallel circuit of two OTPM in series with a resistance. A high voltage stochastically produces a breakdown in one of the two OTPM first, which then reduces the voltage drop across the parallel OTPM circuit to prevent further breakdown events. The experimental results of differential OTPM PUF binary string generation show essentially unbiased randomness to demonstrate excellent resistance to supply voltage variation. Ideal uniqueness and reproducibility are observed. Thus, our approach enables PUF implementation with standard voltage supply tolerance and negligible post-processing.

Highly Reliable Multiport PUF Circuit Based on MOSFET Zero Temperature Coefficient Point

By using processing variations in the unitcircuits of the same structures and design parameters during manufacturing, Physical unclonable function (PUF) generates security keys with characteristic of uniqueness, randomness and unclonability. In this paper, a highly reliable multiport PUF scheme was proposed based on MOSFET Zero temperature coefficient (ZTC) point. It consists of input register, deviation-current generating module, arbiter array and obfuscation circuit. After reconfiguring deviation-current generating module by applying different input challenges, the PUF circuit updates keys without physical replacement. And multi-bit keys can be generated in one clock cycle. In TSMC-LP 65nm CMOS technology, the layout of 64-port reconfigurable PUF occupies 131μm×242μm with custom designing. Experimental results show that the PUF circuit has good statistical characteristic of uniqueness and randomness. It exhibits high reliability of 98.2% with respect to temperature variation from -40°C to 125°C and supply voltage variation from 1.08V to 1.32V, indicating that it can be reliably and effectively used in information security field.

A Reliable Strong PUF Based on Switched-Capacitor Circuit

This paper presents a highly reliable and invasive-attack-resistant switched-capacitor (SC) strong physical unclonable function (PUF), which can offer an extremely large number of challenge–response pairs. Two symmetrical capacitor arrays that are controlled by challenges are used to realize the strong ability of SC PUF. The mismatch created by the capacitor arrays in real fabrication is sampled by an SC circuit and further amplified by a latch-styled sense amplifier. By covering the entire chip with the metallic transmission lines connected to the sampling capacitor, the PUF can resist invasive attacks. To provide highly reliable responses, a built-in self-test (BIST) strategy is also adopted. A test capacitor is embedded in the PUF circuits to automatically test the capacitance deviation of the SC circuit. Only when the capacitance deviation is large, the output of the PUF is selected for use. The proposed strong SC PUF circuit is fabricated and verified using HJ standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that after using the BIST strategy, the bit error rate is less than $10^{-9}$ when the ratio of the selected responses is 19.6% for the PUF instances in our test.

Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices

Field programmable gate array (FPGA) technology is being adopted in many digital systems, hence the demand for security increases, especially when intrinsic vulnerabilities of programmable devices jeopardise the intellectual properties (IPs). New high and medium-end FPGA devices have built-in mechanisms that, exploiting encryption primitives, are able to avoid IP piracy by preventing cloning and reverse engineering, but low-end FPGA families still lack security solutions. Recently, in the literature, a great researching effort has been done on physically unclonable functions (PUFs), which are eligible to be a fundamental means for authenticating integrated circuits. They can be adopted to guarantee protection against IP violations by implementing locking finite state machines (FSMs) on any device. In this paper, we show two implementations of the Anderson PUF, a good scalable and high reliable PUF architecture, on the Xilinx Spartan-3E family, which can be adopted to introduce the locking mechanism. In the experimental result, we show the quality parameters for signatures generated from proposed Anderson PUFs and the overhead introduced by the locking mechanism through an FSM.