Reliable Physical Unclonable Function Research Articles

Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices

Field programmable gate array (FPGA) technology is being adopted in many digital systems, hence the demand for security increases, especially when intrinsic vulnerabilities of programmable devices jeopardise the intellectual properties (IPs). New high and medium-end FPGA devices have built-in mechanisms that, exploiting encryption primitives, are able to avoid IP piracy by preventing cloning and reverse engineering, but low-end FPGA families still lack security solutions. Recently, in the literature, a great researching effort has been done on physically unclonable functions (PUFs), which are eligible to be a fundamental means for authenticating integrated circuits. They can be adopted to guarantee protection against IP violations by implementing locking finite state machines (FSMs) on any device. In this paper, we show two implementations of the Anderson PUF, a good scalable and high reliable PUF architecture, on the Xilinx Spartan-3E family, which can be adopted to introduce the locking mechanism. In the experimental result, we show the quality parameters for signatures generated from proposed Anderson PUFs and the overhead introduced by the locking mechanism through an FSM.

Cherry-Picking Reliable PUF Bits With Differential Sequence Coding

Silicon physical unclonable functions (PUFs) produce a sequence of response bits from chip-unique manufacturing variations. Since the response bits are physically derived, there is noise present. To generate bit-exact cryptographic keys, error correction algorithms are used. The error correction is typically split into small processing blocks to reduce implementation complexity. The reliability of PUF responses varies from bit to bit, but there has been very little work so far that mathematically analyzes the effect of the block size on the reliability of PUF response sequences. We use the information theoretical concept of typicality to show that the probability of drawing an unreliable sequence decreases exponentially with the block size. We present differential sequence coding that scales efficiently across larger block sizes without having the super-linear increase in decoding complexity of prior approaches. It scans the entire PUF response sequentially and then only operates on one single, maximally reliable, block to generate the cryptographic key. Our sample FPGA implementation with a convolutional code is designed for a popular SRAM PUF scenario. It generates a 128-bit key for an average input bit error probability of 15% with an output bit error probability of $6.14 \cdot 10^{-9}$ and only uses 974 PUF bits and 1, 108 helper data bits. There are 36% less PUF bits and 71% less helper data bits than the best previous individual results in both criteria without increasing the implementation size of the key generation module noticeably.

Physical Unclonable Function Exploiting Sneak Paths in Resistive Cross-point Array

The physical unclonable function (PUF) is a promising innovative hardware security primitive that leverages the inherent randomness in the physical systems to produce unique responses upon the inquiry of challenges, thus the PUF could serve as a fingerprint for device authentication. In this paper, we propose a novel PUF implementation exploiting the sneak paths in the resistive cross-point (X-point) array, as a hardware security primitive. The entanglement of the sneak paths in the X-point array greatly enhances the entropy of the physical system, thereby increasing the space of challenge-response pairs to make a strong PUF. The X-point PUF characteristics, such as uniqueness and reliability, are experimentally evaluated on the fabricated $12 \times 12$ cross-point arrays based on the Pt/HfO x /TiN structure. The measurement results show that the average inter-Hamming distance of the response bits is around 46.2% across 28 different arrays, showing sufficient uniqueness. The measurement results also demonstrate that 0% intra-Hamming distance (or 100% reliability) of the response bits can be maintained more than 7.2 h at 100 °C (or equivalently ten years at 40 °C). This paper demonstrates the feasibility of using X-point PUF as a lightweight and reliable PUF for device authentication.

Ultra‐energy‐efficient temperature‐stable physical unclonable function in 65 nm CMOS

Physical unclonable functions (PUFs) are promising hardware security primitives suitable for resource-constrained devices requiring lightweight cryptographic methods. This Letter proposes an ultra-low-power and reliable PUF based on a customised dynamic two-stage comparator operating in the sub-threshold region. The proposed PUF is implemented in a standard 65 nm CMOS technology and validated through Monte-Carlo simulations. Evaluation results show a worst-case reliability of 98.3% over the commercial temperature range of 0°C to 85°C and 10% fluctuations in supply voltage. In addition, the 128-bit PUF array consumes only 1.33 μW at 1 Mb/s, which corresponds to 10.3 fJ/bit, being the most energy-efficient design to date.

Design of a reliable PUF circuit based on R–2R ladder digital-to-analog convertor**Project supported by the National Natural Science Foundation of China (Nos. 61474068, 61404076, 61274132), the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), and the K. C. Wong Magna Fund in Ningbo University, China.

A novel physical unclonable functions (PUF) circuit is proposed, which relies on non-linear characteristic of analog voltage generated by R–2R ladder DAC. After amplifying the deviation signal, the robustness of the DAC-PUF circuit has increased significantly. The DAC-PUF circuit is designed in TSMC 65 nm CMOS technology and the layout occupies 86.06 × 63.56 μm2. Monte Carlo simulation results show that the reliability of the DAC-PUF circuit is above 98% over a comprehensive range of environmental variation, such as temperature and supply voltage.

Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells

Physical unclonable functions (PUFs) are circuits that produce outputs determined by random physical variations from fabrication. The PUF studied in this paper utilizes the variation sensitivity of static random access memory (SRAM) data retention voltage (DRV), the minimum voltage at which each cell can retain state. Prior work shows that DRV can uniquely identify circuit instances with 28% greater success than SRAM power-up states that are used in PUFs [1]. However, DRV is highly sensitive to temperature, and until now this makes it unreliable and unsuitable for use in a PUF. In this paper, we enable DRV PUFs by proposing a DRV-based hash function that is insensitive to temperature. The new hash function, denoted DRV-based hashing (DH), is reliable across temperatures because it utilizes the temperature-insensitive ordering of DRVs across cells, instead of using the DRVs in absolute terms. To evaluate the security and performance of the DRV PUF, we use DRV measurements from commercially available SRAM chips, and use data from a novel DRV prediction algorithm. The prediction algorithm uses machine learning for fast and accurate simulation-free estimation of any cell's DRV, and the prediction error in comparison to circuit simulation has a standard deviation of 0.35 mV. We demonstrate the DRV PUF using two applications-secret key generation and identification. In secret key generation, we introduce a new circuit-level reliability knob as an alternative to error correcting codes. In the identification application, our approach is compared to prior work and shown to result in a smaller false-positive identification rate for any desired true-positive identification rate.