Through-silicon Via Reliability Research Articles

Reliability Simulation Analysis of TSV Structure in Silicon Interposer under Temperature Cycling.

As semiconductor integration scales expand and chip sizes shrink, Through Silicon Via (TSV) technology advances towards smaller diameters and higher aspect ratios, posing significant challenges in thermo-mechanical reliability, particularly within interposer substrates where mismatched coefficients of thermal expansion exacerbate issues. This study conducts a thermo-mechanical analysis of TSV structures within multi-layered complex interposers, and analyzes the thermal stress behavior and reliability under variable temperature conditions (-55 °C to 85 °C), taking into account the typical electroplating defects within the copper pillars in TSVs. Initially, an overall model is established to determine the critical TSV locations. Sub-model analysis is then employed to investigate the stress and deformation of the most critical TSV, enabling the calculation of the temperature cycle life accordingly. Results indicate that the most critical TSV resides centrally within the model, exhibiting the highest equivalent stress. During the temperature cycling process, the maximum deformation experiences approximately periodic variations, while the maximum equivalent stress undergoes continuous accumulation and gradually diminishes. Its peak occurs at the contact interface corner between the TSV and Redistribution Layer (RDL). The estimated life of the critical point is 3.1708 × 105 cycles. Furthermore, it is observed that electroplating defect b alleviates thermal stress within TSVs during temperature cycling. This study provides insights into TSV thermal behavior and reliability, which are crucial for optimizing the design and manufacturing processes of advanced semiconductor packaging.

A novel plating bath device for reducing surface copper thickness and improving wafer-scale uniformity

Through silicon via (TSV) technology plays a pivotal role in three-dimensional integrated circuits. However, excessive surface thickness and uneven wafer plating during TSV copper electroplating pose significant challenges to TSV reliability. This paper proposes a novel rotating cathode electroplating technique that utilizes flow field induction by a rotating cathode to significantly reduce the surface copper thickness by approximately 8 μm, leading to improved uniformity of wafer-scale electroplating and facilitating rapid TSV filling. This study focuses on the impact of cathode rotation speed and chip position on TSV filling quality. The experimental findings demonstrate that increasing the cathode rotation speed reduces the diffusion layer thickness, thereby enhancing filling quality. Additionally, variations in chip position influence surface copper thickness. The introduction of bis(3-sulfopropyl) disulfide accelerant expedites the filling process, boosts the filling ratio, and enables defect-free TSV filling. This study offers valuable insights into the wafer-scale TSV electroplating process and facilitates the optimization of parameter settings during electroplating.

Interface Reliability Modeling of Coaxial Through Silicon Via Based on WOA-BP Neural Network

Abstract Due to the complex structure and thermal mismatch of coaxial through silicon via (TSV), cracks easily occur under thermal load, leading to interface delamination or spalling failure. The reliability issue of coaxial TSV is important for its application in three-dimensional packaging, so it is of great significance to predict the crack trend and evaluate the reliability of coaxial TSV. In this paper, an algorithm model with the combination of whale optimization algorithm (WOA) and back propagation (BP) neural network for the reliability prediction of coaxial TSV is proposed. Based on finite element method (FEM), the training and validation datasets of the energy release rates (ERR) of the crack at the critical interface are calculated to construct the deep learning neural network. Six key structure parameters affecting the reliability of coaxial TSV are selected as the input values of the BP neural network. The maximum relative error of whale optimization algorithm optimized back propagation (WOA-BP) neural network model is 0.88%, which is better than the prediction results of the traditional BP and genetic algorithm (GA) optimized BP models. The WOA-BP neural network model was also compared with BP and GA-BP neural network models with four error metric models. It is verified that WOA-BP neural network model has the best prediction performance. The proposed model can be used to achieve improved prediction accuracy for the interface reliability of coaxial TSV under complex structural conditions since it has higher accuracy and stronger robustness.

RLARA: A TSV-Aware Reinforcement Learning Assisted Fault-Tolerant Routing Algorithm for 3D Network-on-Chip

A three-dimensional Network-on-Chip (3D NoC) equips modern multicore processors with good scalability, a small area, and high performance using vertical through-silicon vias (TSV). However, the failure rate of TSV, which is higher than that of horizontal links, causes unpredictable topology variations and requires adaptive routing algorithms to select the available paths dynamically. Most works have aimed at the congestion control for TSV partially 3D NoCs to bypass the TSV reliability issue, while others have focused on the fault tolerance in TSV fully connected 3D NoCs and ignored the performance degradation. In order to adequately improve reliability and performance in TSV fully connected 3D NoC architectures, we propose a TSV-aware Reinforcement Learning Assisted Routing Algorithm (RLARA) for fault-tolerant 3D NoCs. The proposed method can take advantage of both the high throughput of fully connected TSVs and the cost-effective fault tolerance of partially connected TSVs using periodically updated TSV-aware Q table of reinforcement learning. RLARA makes the distributed routing decision with the lowest TSV utilization to avoid the overheating of the TSVs and mitigate the reliability problem. Furthermore, the K-means clustering algorithm is further adopted to compress the routing table of RLARA by exploiting the routing information similarity. To alleviate the inherent deadlock issue of adaptive routing algorithms, the link Q-value from reinforcement learning is combined with the router status based in buffer utilization to predict the congestion and enable RLARA to perform best even under a high traffic load. The experimental results of the ablation study on simulator Garnet 2.0 verify the effectiveness of our proposed RLARA under different fault models, which can perform better than the latest 3D NoC routing algorithms, with up to a 9.04% lower average delay and 8.58% higher successful delivered rate.

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

Parameter analysis and electrochemical properties of 4,6-Dimethyl-2-mercaptopyrimidine for mitigating Cu prominence in through silicon vias filling

Through silicon via (TSV) is the core technology that implements three-dimensional (3D) integrated packaging in integrated circuits. Electrodeposition defects affect the reliability of TSVs. In particular, the surface Cu protrusions can lead to structural deformations, which significantly affect the reliability of TSVs. In this study, 4,6-Dimethyl-2-mercaptopyrimidine (DMP) is studied as a leveller additive for TSV electroplating, along with the effect of the deposition parameters on the TSV filling process and surface morphology. To evaluate the filling performance of DMP, linear sweep voltammetry (LSV) is performed to investigate how the additives affect the filling mechanism. Finally, the conditions of this levelling agent in TSV plating are predicted based on LSV curves and validated using plating experiments.

Modeling and Characterization of Annealing-Induced Cu Protrusion of TSVs With Polyimide Liner Considering Diffusion Creep Behavior

Polymer liner has been used in through-silicon-vias (TSVs) for smaller parasitic capacitance and better thermo-mechanical performance. For the application in heterogeneous integrated systems, it is critical to study the thermal reliability of such TSVs in both theoretical modeling and experimental characterization. Among the numerous reliability challenges, the Cu protrusion phenomenon of TSVs is one of the most severe issues, which can lead to cracks and delamination in integrated systems. In this article, the annealing-induced Cu protrusion of polyimide (PI) liner TSVs is studied by experiments and simulations. PI-TSVs are fabricated and the Cu protrusion at various annealing conditions is characterized. Finite element analysis (FEA) is carefully carried out taking into account the diffusion creep rate model, and the deviations between FEA and experiment results of protrusion heights are less than 3%. Besides, the deformation procedure and the creep behavior of Cu pillars during annealing are analyzed. Based on the proposed FEA model, comprehensive parametric analyses are conducted to study the effects of different annealing conditions on the Cu protrusion heights, which are helpful to understand and improve the thermal reliability of PI-TSVs.

Experimental research on performance degradation of TSV microstructure under thermal cycling, vibration and electrical stress

Through‑silicon-via (TSV) microstructure is the key structure of 3D integrated packaging, and its reliability during service plays a very important role in the long-term reliable operation of the chip. However, the failure mechanism and reliability evaluation of the TSV structure in the service process of the chip have not been fully elucidated. Chips inevitably bear various stresses during the service process, such as thermal stress, vibration stress, electrical stress, etc. In this paper, a TSV reliability test chip that can be easily loaded with various stresses was designed first, and the resistivity of the TSV microstructure was tested. It is found that the resistivity of TSV has a significant scale effect. Then, thermal cycling, vibration and electromigration tests were carried out, and the failure mode, performance degradation trend and failure distribution of TSV microstructure under thermal cycling, vibration and electrical stress were analyzed. Finally, the failure analysis of the tested chip was carried out by scanning electron microscope (SEM) and high-resolution industrial micro-CT, and the potential failure mechanism were analyzed and discussed.

Effects of multi-cracks and thermal-mechanical coupled load on the TSV reliability

Three-dimensional (3D) integrated packaging technology is gradually moving from the laboratory to the market. Through silicon via (TSV) is the most critical structural unit in 3D integrated packaging. However, during the TSV manufacturing process flow and its service process, many micro cracks will be generated in the TSV microstructure. The multi-cracks seriously threaten the reliability of the TSV and affect the device performance and service life. The existing literature often focus on a single crack under thermal load alone, which obviously does not match the actual situation and leads to larger analysis errors. Based on the theory of elastoplastic fracture mechanics and multi-physics coupling analysis, this paper explored the effects of multi-cracks and thermal-mechanical coupled load on the reliability of TSVs using numerical analysis. Using the J integral value as the indicator, the effects of crack numbers, crack locations, crack lengths, crack propagation directions and thermal-mechanical coupled load on the crack propagation of TSV structures were studied. Based on the research results, suggestions were made for TSV structure design and manufacturing process optimization. The main goal of this paper is to explore the influence of cracks and thermal-mechanical coupled loads on TSV microstructure through numerical analysis. Due to the micro-scale of the TSV structure, the above targets are difficult to obtain through experimental tests. The research methods and results of this paper can provide important references for the reliability evaluation and optimization design of TSV microstructures.

Study on atomic migration of copper through-silicon-vias with Bosch scallops

In three-dimensional integration, atomic migration is a critical challenge for through‑silicon-via (TSV) reliability, especially under high electric current and thermal stress. Meanwhile, Bosch scallops, as the byproduct of Bosch process, can cause stress concentration around them, which further undermines TSV reliability. In this paper, the migration behavior of copper TSVs with Bosch scallops is assessed in an operational scenario using a migration model, while residual stress is taken into account. The possible failure location is studied first, followed by the mechanism of different migration modes. It is shown that the effect of stress on atomic migration manifests itself earlier than that of electric current. Besides, the periodic concentration fluctuation arises along the interface with Bosch scallops, and the amplitude of fluctuation increases as the width of Bosch scallops increases. Furthermore, the impacts of operation temperature and process temperature are investigated to guide the optimization design for the robust TSV structure.

Cu Protrusion of Different through-Silicon via Shapes under Annealing Process

The through-silicon via (TSV) 3D integration method has become one of the most widely used techniques for achieving system-level integration for applications that require smaller package sizes, higher interconnection density and high performance. This is because the TSV fabrication technology provides the mechanism for facilitating communications between various layers of the 3D integration system and for interconnecting stacked devices at wafer-level. Although there are several reported studies on TSV 3D integration R&D, with most of these studies focused on the improvement of TSV fabrication process, there are very limited in-depth studies associated with the TSV reliability issues and challenges. In this paper, we investigate the effect of TSV geometries on the associated TSV reliability factors. Different TSV geometries including I-type, tapered, elliptical, triangular, quadrangular and circular shapes (with same volume) are investigated to find the most reliable structure under annealing process. The results show that the tapered TSV shape releases thermo-mechanical stress more uniformly than other shapes and larger top surface shows better reliability.

Reliability Simulation and Life Prediction of TSV Under a Thermoelectric Coupling Field in a 3D Integrated Circuit

The reliability of through silicon via (TSV) in a 3-dimensional integrated circuit (3D IC) determines whether the electronic system can operate continuously and steadily. The finite element method was adopted to study the response of TSV to thermoelectric coupling, the effect of different dielectric layer materials and the filling degree of carbon nanotubes (CNT) on TSV reliability were investigated, respectively. Through orthogonal simulation experiments, the high reliability of a type of TSV with benzocyclobutene (BCB) dielectric layer and filling by a coaxial hybrid CNT bundle was verified, and its lifetime was predicted by the failure of the physical model. The simulation results show that the most important influence factor to TSV reliability is the depth-to-width ratio, the second important factor is the choice of dielectric material, and the least important factor is the filling degree of CNT. The parameter values with the optimum reliability are as follows: the depth-to-width ratio of copper column is 20, the dielectric material is BCB, and the CNT filling degree is 4–8%.

Effects of anisotropy on the reliability of TSV microstructure

Through silicon via (TSV) is a very important interconnect structure in 3D integrated packaging, and its reliability directly affects the reliable service life of 3D integrated packaging devices. TSVs contain multiple material interfaces, and there is a large thermal mismatch between the materials, which poses a serious challenge to its reliability under thermal cycling loads. In the available literatures, silicon (substrate) and copper (filler) materials have often been considered as isotropic materials for research and analysis. However, for micron-scale TSV structures, the orientation of silicon crystals and the orientation of copper grains can have a non-negligible effect on the stress and strain distribution and interface crack propagation of the structure, which in turn significantly affects the overall reliability of the TSV structure. This article explored in detail the influence of the anisotropy of silicon and copper on the reliability of TSVs, and particularly focused on the coupled effect of anisotropic of silicon and copper. In addition, the influence of copper plasticity was also analyzed.

Research on fatigue of TSV-Cu under thermal and vibration coupled load based on numerical analysis

The three-dimensional (3D) integrated packaging technology based on through-silicon-via (TSV) is recognized as a new packaging technology which is most likely to exceed Moore's Law and complies with the requirements of smaller size, higher performance, lighter weight and lower power consumption. However, its failure mechanism and reliability problems during the long-term service process have not been fully elucidated, which hinders its widespread application. There is plenty of literature about the reliability of the TSV structure under thermal load, but the literature considering vibration loads is extremely rare. On the other hand, most of the previous literature focuses on the reliability of the TSV structure in manufacturing processes (such as annealing), but little attention was paid to their reliability assessment during service life. As the fundamental structure of 3D integrated packaging, TSV reliability will undoubtedly play a pivotal role in the long-term service reliability of the chip. The TSV structure needs to withstand various complex loads during service, such as thermal load, vibration load, electric load, etc., so it is necessary to consider the coupling of various loads to scientifically and effectively evaluate its reliability life. In this paper, the fatigue theory and multi-field coupled numerical analysis theory were summarized in detail. On this basis, a numerical analysis method for thermal-vibration coupling of TSV copper (TSV-Cu) was proposed. The typical TSV microstructure model was established and the fatigue life of electroplated copper under thermal and vibration coupled loads was calculated based on E-N curve. The influence of loading parameters on fatigue life was explored and compared. The results show that the effects of different load forms and parameter conditions on the fatigue life of TSV-Cu are significantly different.

Comparative evaluations on scallop-induced electric-thermo-mechanical reliability of through-silicon-vias

Sidewall scallops of through-silicon-vias (TSVs) formed during the Bosch etching process will bring serious challenges to TSV reliability. In this paper, the impact of sidewall scallops on the electric-thermo-mechanical reliability of TSVs is investigated, where the self-heating effect of TSV conductor and the residual stress caused by the deposition of different TSV layers are involved. Utilizing multi-physics field analysis with sub-modeling technique, the electric-thermo-mechanical reliability of TSVs is assessed by different indicators, including current density, temperature, heat flux and von Mises stress. It is shown that, the presence of sidewall scallops will result in periodic fluctuations in terms of current density, heat flux and stress distributions, which will further undermine TSV reliability. However, the comparative study between TSVs with polyimide liner and conventional SiO2 liner demonstrates that, employing polyimide as TSV liner can eliminate various scallop-induced fluctuations and improve the electric-thermo-mechanical reliability of TSVs effectively.

Cellular Automata Based Test Design for Coherence Verification in 3D Caches

To provide high vertical interconnection density between device tiers, Through Silicon Via (TSV) offers a promising solution in 3D caches. It reduces the length of global interconnection and ensures high speed cache memory access. Maintaining coherency of shared data in such caches is, however, very crucial and, therefore, demands that the reliability and accuracy of TSVs as well as the cache coherence controller (CC) are to be ensured. In the current work, we propose an elegant test solution for at-speed detection of stuck-at-faults in TSVs (offline test) as well as verification for the functioning of CC (online test). The proposed test structure is designed around the modular and cascadable structure of Cellular Automata (CA) to achieve a cost-effective realization of test and coherence verification in 3D caches with high degree of scalability. It ensures correct decisions in more than 71% cases even if the test hardware is subjected to single stuck-at-fault.

Copper-silicon carbide composite plating for inhibiting the extrusion of through silicon via (TSV)

For 3D packaging using TSV technology, it is required various techniques such as forming via holes on a wafer, filling conductive materials and interpretation of TSV reliability etc. Among them, solving the issue of reliability are standing out as a big problem for reaching commercialization in the future. When the conductive material filled in the TSV is expanded by the high-temperature process during the packaging process, it breaks the insulating layer and the metal interconnection which exist on via hole by extruding from the surface of the Si wafer. In this study, in order to suppress the Cu extrusion, electroplating was attempted by adding silicon carbide powder having almost no difference in thermal expansion coefficient with the Si chip in the Cu electroplating solution. As a result, the extrusion height of Cu-SiC was about 164 nm that is a height corresponding to 14.6% of the extrusion height of Cu. This is considered to be the result of extremely effectively suppressing the extrusion phenomenon after annealing by adding SiC powder with a low coefficient of thermal expansion into the conventional Cu plating solution.

Study on copper protrusion of through-silicon via in a 3-D integrated circuit

The through-silicon via (TSV) approach is crucial for three-dimensional integrated circuit (3-D IC) packaging technology. However, there are still several challenges in the TSV fabrication process. One of the widely known challenges is via protrusion phenomenon. Annealing a TSV wafer makes the copper (Cu) TSVs under high stress and may form a protrusion where the Cu is extruded out of the TSV structure. The phenomenon occurs because of the large mismatch in the coefficient of thermal expansion between Cu via and silicon (Si) layer. Cu protrusion is able to cause crack, delamination of the back-end-of-line and short circuit of the chip, thus, it is a dangerous threat to the metal layer interconnect. Experiments are conducted to characterize the protrusion using several techniques. Scanning electron microscope is used to observe the protrusion topography and measure the height. Electron backscatter diffraction (EBSD) technique is implemented to study the grain size distribution, local texture and microstructure evolution inside Cu vias. For the experiment, arrays of 10 μm diameter TSVs are fabricated and annealed in argon gas environment in six different temperatures. In this paper, finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions. Correlation between numerical results and experimental data is then performed. Based on the verified FEA methodology, several parametric studies are then conducted, including the effects of annealing temperature on Cu protrusion, residual stress distributions of TSV structures. The simulation results are helpful to understand and solve the key problem in TSV fabrication process and reliability challenge.

Sulfur-Containing Additives for Mitigating Cu Protrusion in Through Silicon via (TSV)

Since the introduction of through silicon via (TSV) technology, Cu electrodeposition methods for defect-free and fast TSV filling have been investigated, such as by using various organic additives or controlling deposition conditions. However, there are few studies on regulating Cu protrusion of TSV, which may occur in subsequent semiconductor processes and strongly influences the reliability of Cu TSV. In this study, we used 2-mercapto-5-benzimidazole sulfonic acid (2M5S) and thiourea (TU) as separate additives during TSV filling to mitigate Cu protrusion. The electrochemical behavior of 2M5S and TU showed that they interacted strongly with iodide ions (leveler) to promote or suppress Cu electrodeposition, respectively. The uniformity of TSV filling was also influenced by the additives. During Cu electrodeposition, these additives were incorporated into the Cu matrix to induce the pinning effect and mitigate Cu protrusion. The degree of Cu protrusion was effectively reduced by 84.9% and 69.2% with 2M5S and TU, respectively, when compared to the absence of these additives.

High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoC

Wireless interconnects using near-field inductive coupling (NFIC) enables contactless vertical communications necessary for the design of energy efficient and robust 3-D manycore systems. However, the achievable performance, energy efficiency, bandwidth, and associated area overhead of NFICs are intertwined imposing significant design challenges and tradeoffs to explore the optimum link configuration. To address these challenges, in this paper, we propose a holistic design approach for exploring energy-efficient NFICs and target to exploit the benefits of the NFICs in the context of efficient and reliable network-on-chip (NoC) design. The proposed design framework employs statistical link analysis to select optimum NFIC-link configuration and is significantly more efficient in terms of energy efficiency and area overhead compared to the state-of-the-art counterparts. We demonstrate that 3-D NoCs incorporating NFIC-enabled links outperform through-silicon-via (TSV) counterparts. In addition, the overall reliability of TSV- and NFIC-enabled hybrid 3-D NoC is significantly better than only TSV-based NoCs in order to counteract the electromigration and workload-induced stress challenges.