Reliability Of Phase Change Memory Research Articles

WN coating of TiN electrode to improve the reliability of phase change memory

The heating electrode contact (HEC), as the key part for collecting current and transferring heat in phase change memory (PCM), tends to be unevenly oxidized by the external SiO2 coating layer during manufacturing and fatigue, resulting in negative effects on the performance of PCM. In this paper, WN film is used as the protective layer to avoid oxidation of TiN HEC. The RESET/SET current of PCM cells is reduced because of the oxygen barrier and heat preservation effect of WN film. In the endurance test of HEC, the cycle times of TiN electrode double-coated by WN can reach 1012, which is significantly higher than the electrode double-coated by SiO2. Besides, the endurance characteristics of PCM cells with this new structure of HEC are proved to be better.

Enhancing the Data Reliability of Multilevel Storage in Phase Change Memory with 2T2R Cell Structure.

Multilevel storage and the continuing scaling down of technology have significantly improved the storage density of phase change memory, but have also brought about a challenge, in that data reliability can degrade due to the resistance drift. To ensure data reliability, many read and write operation technologies have been proposed. However, they only mitigate the influence on data through read and write operations after resistance drift occurs. In this paper, we consider the working principle of multilevel storage for PCM and present a novel 2T2R structure circuit to increase the storage density and reduce the influence of resistance drift fundamentally. To realize 3-bit per cell storage, a wide range of resistances were selected as different states of phase change memory. Then, we proposed a 4:3 compressing encoding scheme to transform the output data into binary data states. Therefore, the designed 2T2R was proven to have optimized storage density and data reliability by monitoring the conductance distribution at four time points (1 ms, 1 s, 6 h, 12 h) in 4000 devices. Simulation results showed that the resistance drift of our proposed 2T2R structure can significantly improve the storage density of multilevel storage and increase the data reliability of phase change memory.

Exploiting Resistance Drift Characteristics to Improve Reliability of LDPC-Assisted Phase-Change Memory

Phase-change memory (PCM) as emerging non-volatile memory has attracted more attention and considered as the promising replacement of the main memory. PCM has shown good scalability and high storage density, but data storage reliability has become a challenge and concern. When data are written into PCM cells by a phase transition between amorphous and crystalline, the resistance of each state drifts as the increase of storage time due to structural relaxation. As a result, raw bit error rates (RBER) become higher and higher, severely degrading the data storage reliability (i.e., an important problem in PCM). In this paper, we first find that high error percentage exists between the full amorphous and amorphous states in multilevel cell (MLC) PCM via a preliminary experiment, which is the main factor leading to high RBER. Then, we analyze why this phenomenon exists in PCM from the view of the resistance drift. Finally, by exploiting the resistance drift characteristics, we propose drift compensation and drift-aware LDPC decoding schemes to improve reliability of PCM. Simulation results show that the proposed schemes can significantly reduce the RBER and LDPC decoding iterations.

Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement

With the scaling limitations and increasing leakage power of the existing charge-based memories, next-generation memory technologies to overcome the issues are in development. Among the various emerging memories, phase change memory (PCM) is considered as a promising candidate due to its scalability potential and negligible leakage power. For enhanced storage density, the multilevel cell (MLC) operation has been proposed for PCM. This, however, comes at cost of poor reliability, write energy increase and performance degradation. Unlike DRAM, the MLC PCM has a much higher soft error rate due to the resistance drift phenomenon. Error correction code (ECC) schemes can be utilized to improve the MLC PCM reliability, however, this would lead to a lower storage density and an increase in write energy and latency. The iterative programming required for the MLC PCM also degrades its energy efficiency and performance. This paper introduces a simple yet effective encoding scheme to mitigate the problems of the MLC PCM. By using a simple XOR-based encoding, the proposed architecture minimizes the most drift-prone state in the data. The method divides the original data into several encoding blocks and analyzes initial pattern frequencies for each 2-bit pattern. Based on the initial pattern frequencies, the inputs for the XOR encoding are selected that result in minimal frequency of the drift-prone state. This considerably enhances the MLC PCM reliability, leading to a high storage density with a reduced ECC overhead. The energy efficiency and performance are also improved due to reduction in iterative current pulses and ECC overhead. The simulation results show a reduction of about $10^{5}$ X in soft error rate. The improvements in energy efficiency and performance over the conventional 4-level cell (4LC) PCM are 11.5% and 31.9%, respectively.

Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy Efficiency

Next-generation memories have been actively researched to replace the existing memories like DRAM and flash in deep sub-micron process technology. Unlike the conventional charge-based memories, next-generation memories utilize the resistive properties of different materials to store and read a data. Among the next-generation memories, Phase Change Memory (PCM) is seen as a good choice for future memory systems, given its good read performance, process compatibility and scaling potential. To enhance the storage density, multi-level cell (MLC) operation is seemed promising which can store more than one bit in each PCM cell. However, MLC operation significantly degrades the reliability of PCM, thus requiring a strong Error Correction Code (ECC) to guarantee correct memory operation. The use of heavyweight ECC comes at cost of significant degradations in storage density, performance and energy efficiency. In this article, we propose a heterogeneous PCM architecture which uses both multi-level cell and single-level cell (SLC) together for a single word line. With highly-reliable SLC cells, the overall array reliability is enhanced. To improve the reliability further, a dynamic self-encoding/decoding scheme is performed before the data is written to the PCM cells. The dynamic scheme automatically determines the locations of MLC and SLC cells and sets the corresponding resistance levels to be programmed. Since the proposed encoding/decoding scheme does not require any additional stages or storages for encoding and decoding, the overhead is negligible. The improved reliability allows to use lighter ECC scheme which in turn helps to improve performance and energy efficiency of the MLC PCM. The experimental results show that the reliability is improved by approximately <inline-formula><tex-math notation="LaTeX">$10^6$</tex-math></inline-formula> times compared to the conventional 4LC and more than <inline-formula><tex-math notation="LaTeX">$10^3$</tex-math></inline-formula> times compared to the existing encoding methods. The performance improvement is 21.5 percent over the conventional 4LC and is more than 4.1 percent higher than the prior encoding techniques. The proposed method is 30.3 percent more energy efficient than the conventional 4LC and this is similar or higher than other energy efficiency improvement methods.

Crystallization behavior and electrical characteristics of Ga–Sb thin films for phase change memory

In this work, we investigated the structural and conductivity stability of Ga–Sb thin films for phase change memory (PCM). The mass density and thickness change are significant for stability and reliability of PCM. The Ga–Sb thin films were deposited on SiO2/Si (100) wafer using magnetron co-sputtering method. Phase identification revealed that nanoscale face center cubic structure GaSb and rhombohedral structure Sb formed in Ga–Sb thin films, the formation of phase Sb was more obvious in Ga20Sb80. Ga–Sb film exhibits an unusual behavior upon crystallization with less mass density and thickness change. The microstructure of Ga45Sb55 thin films improved their structural (density and film thickness) characteristics: the crystal growth of {111} and {110} oriented grains in Ga–Sb thin films is obvious, the grains growth in Ga45Sb55 thin films was more even and the bonding states in Ga–Sb thin films were more stable. In addition, the conductivity activation energy of Ga–Sb decreased with increasing Sb contents, thus the temperature stability of conductivity was improved. The structure transformation and conductivity activation energy of Ga–Sb phase change materials are in favor of mechanical stresses reduction and reliability enhancement of PCM. This study introduces the influence mechanism of structural and conductivity stability in Ga–Sb thin films and may provide reference for further testing in higher endurance performance phase change materials.

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

The existing charge-based memories like DRAM and flash are reaching their scaling limits. Phase change memory (PCM) is one of the most promising emerging memory technologies due to its good scalability and low leakage power. Multi-level cell (MLC) operation in PCM, which stores two or more bits in a single cell, is necessary to achieve a high storage density. However, a reduced resistance range in multiple storage levels of MLC PCM, introduces a lot of soft errors because of the resistance drift phenomenon. The poor reliability of MLC PCM requires strong error correction codes (ECC) which could severely degrade the storage density and performance. In this paper, we propose a cost-effective reliable MLC PCM architecture for improving MLC PCM reliability, storage density and performance. The proposed architecture exploits the data-dependent nature of resistance drift problem to reduce the ECC overhead. A simple state mapping is used to generate virtual data, which is half of the actual data size. ECC parity bits are generated based on virtual data bits instead of actual message bits, thus resulting in a reduced number of cells for parity bits. This improves the reliability and storage density of MLC PCM. The performance is also improved by minimizing the ECC overhead. Simulation results show an improvement of about 10 4 times in reliability and 10.9% in storage density compared to a conventional MLC PCM which uses a typical error correction scheme. Performance and energy efficiency are also improved up to 13.7% and 10%, respectively, by the proposed architecture.

RESET current optimization for phase change memory based on the sub-threshold slope

The RESET current (Irst) is a key parameter to characterize power consumption and reliability of phase change memory (PCM) device. And the Optimization of Irst is a classic issue in the investigation of PCM targeting to meet various demands. In this paper, a RESET current optimization method, based on the relationship between the RESET current and the sub-threshold slope (STS), has been presented. Different from the conventional way which uses resistance values and bit yields, the new method that adopting the STS extracted from the V–I characteristics is simple, efficient and non-destructive. Here, the experimental results collected from sample cells of a PCM array confirm that the STS can be an important indicator for RESET current optimization. Furthermore, the voltage stress and endurance performance of the PCM devices operated by different RESET current are also measured, which further prove that the optimal RESET current determined by the new method is beneficial for both power consumption and reliability.

Stability of Sb&lt;sub&gt;2&lt;/sub&gt;Te Crystalline Films for Phase Change Memory

Stability is one of the most important criterions to judge the quality of products, especially for the phase-change memory (PCM), which is regarded as the most promising candidate for next-generation non-volatile memory. Due to the lack of resistance stability, read errors can occur easily and the reliability of PCM will be influenced. Using Sb2Te as a base material, the resistance stability of Sb2Te was studied, and the results indicated that in the whole cooling process, the resistance of Sb2Te crystalline film was extremely steady under different annealing temperatures and different cooling rates. To unravel the reason why the resistance of Sb2Te crystalline film has good stability, further study was carried out and the results showed that there was no new diffraction peak in the XRD pattern, and the HRTEM images showed the similar hexagonal phase for the films under different annealing temperatures. Moreover, it was observed that the resistance in Sb2Te-based PCM device was still stable for crystalline state and amorphous state. These results revealed that the stability of Sb2Te crystalline films at a micro level and the stability of microscopic structure resulted in the stability of resistance. Therefore, based on the present study, the stability of phase-change material Sb2Te can be applied to exploit more reliable PCM for near-future application.

(Invited) Bipolar Switching of Phase Change Memory for Enhanced High-Temperature Stability

Phase change memory (PCM) devices are among the most mature technology for storage class memory and embedded memory for, e.g., the internet of things (IoT). One of the key limitation of PCM is the crystallization of the amorphous phase taking place at relatively low temperature, e.g., 150°C for Ge2Sb2Te5(GST) [1]. The low crystallization point prevents the use of PCM in high-temperature applications, such as automotive and embedded chips requiring retention up to 260°C. To overcome the temperature limitations, phase change materials with higher stability against crystallization have been presented, such as C-doped GST [2] and Ge-rich GST [3]. However, increasing the crystallization point raises stability issues for the set (crystalline) state due to the time evolution of the grain boundary structure [4]. Therefore, other techniques to improve the high-temperature reliability of PCM, e.g., by algorithm and/or alternative storage concepts, must be developed.This work addresses the bipolar switching of PCM. Mushroom-type devices with confined bottom electrode (or heater), where subjected to bipolar operation: the application of a positive voltage to a PCM in the amorphous phase leads to threshold switching and set transition to low resistance, while the application of a negative voltage causes a reset transition to high resistance, similar to the one typically observed in resistive switching memory (RRAM). The reset voltage is lower than the melting temperature, thus evidencing that reset transition is not due to a phase change, such as melting and amorphization. Bipolar switching is interpreted by ionic migration of elemental species, such as Ge, Sb and Te in GST. The initial positive voltage causes crystallization with approximately uniform distribution of atomic elements, then the applied negative voltage causes ionic migration driven by the electric field and accelerated by the local Joule heating. In particular, cation-type Ge and Sb migrate toward the top electrode, thus leaving a depleted region in correspondence of the bottom electrode. The high concentration of vacancies and possibly microvoids in the depleted region are responsible for the high resistance which can reach the few GΩ range. Application of a positive voltage results in ionic redistribution and the decrease of resistance. The stability of the bipolar reset state was addressed at both room temperature and high temperature. The bipolar reset state does not show any resistance drift, confirming that the storage concept does not rely on the transition to the amorphous phase. Similarly, there is no evidence for crystallization at high-temperature for the bipolar reset state. While the conventional reset state, obtained under either positive or negative voltage, shows crystallization around 150°C, the bipolar reset show a gradual decline of resistance suggestive of redistribution (e.g., diffusion) of atomic species in the depleted gap. A residual resistance window of 10x is achieved at 250°C, supporting the use of bipolar switching PCM for high temperature application. For instance, bipolar switching PCM might be suitable to sustain retention tests for few minutes at 260°C, which are required for embedded applications [5]. These results might thus open novel application spaces by overcoming the limitations of phase transition in conventional PCM. [1] T. Kato and K. Tanaka, “Electronic properties of amorphous and crystalline Ge2Sb2Te5 films,” Jpn. J. Appl. Phys. 44, 7340 (2005).[2] G. Navarro, et al., “Trade-off Between SET and Data Retention Performance Thanks to Innovative Materials for Phase-Change Memory,” IEDM Tech. Dig. 570 (2013). [3] H. Y. Cheng, et al., “A High Performance Phase Change Memory with Fast Switching Speed and High Temperature Retention by Engineering the GexSbyTez phase Change Material,” IEDM Tech. Dig. 51 (2011). [4] N. Ciocchini, E. Palumbo, M. Borghi, P. Zuliani, R. Annunziata, D. Ielmini, “Modeling resistance instabilities of set and reset states in phase change memory with Ge-rich GeSbTe,” IEEE Trans. Electron Devices 61, 2136 (2014). [5] P. Zuliani, et al., “Overcoming Temperature Limitations in Phase Change Memories With Optimized GexSbyTez,” IEEE Trans. Electron Devices 60, 4020 (2013).

The feasibility of Sn, In, or Al doped ZnSb thin film as candidates for phase change material

The potentials of Sn, In, or Al doped ZnSb thin film as candidates for phase change materials have been studied in this paper. It was found that the Zn-Sb bonds were broken by the addition of the dopants and homopolar Zn-Zn bonds and other heteropolar bonds, such as Sn-Sb, In-Sb, and Al-Sb, were subsequently formed. The existence of homopolar Sn-Sn and In-In bonds in Zn50Sb36Sn14 and Zn41Sb36In23 films, but no any Al-Al bonds in Zn35Sb30Al35 film, was confirmed. All these three amorphous films crystallize with the appearance of crystalline rhombohedral Sb phase, and Zn35Sb30Al35 film even exhibits a second crystallization process where the crystalline AlSb phase is separated out. The Zn35Sb30Al35 film exhibits a reversible phase change behavior with a larger Ea (∼4.7 eV), higher Tc (∼245 °C), better 10-yr data retention (∼182 °C), less incubation time (20 ns at 70 mW), and faster complete crystallization speed (45 ns at 70 mW). Moreover, Zn35Sb30Al35 film shows the smaller root-mean-square (1.654 nm) and less change of the thickness between amorphous and crystalline state (7.5%), which are in favor of improving the reliability of phase change memory.

Impact of Thermoelectric Effects on Phase Change Memory Characteristics

Joule heating in phase change memory (PCM) controls programming characteristics, read disturb, and programming disturb. To optimize the energy consumption and reliability of PCM, a thorough understanding of Joule heating as a function of the electrical operation of the device is thus strongly required. This paper presents a comprehensive characterization of thermoelectric (TE) effects in PCM operated at positive and negative voltage polarity. The impact of polarity was studied for all major temperature-dependent properties of the PCM device, namely, melting, crystallization, ion migration, threshold switching, and holding. It was demonstrated that heating is less efficient under negative voltage, compared with positive voltage. It was also shown that the positive and negative voltages needed to induce all above phenomena display a universal correlation. We propose a unified finite-element model for the PCM, which correctly accounts for the observed polarity-dependent heating and the universal voltage characteristics. The impact of isotropic scaling on TE is finally addressed.

Phase Change Memory Reliability: A Signal Processing and Coding Perspective

Phase change memory (PCM) is a new solid-state memory technology that promises disruptive changes in the way servers and enterprise storage systems are built. Multilevel-cell (MLC) storage is highly desirable for increasing capacity and thus lowering cost-per-bit in memory technologies. In PCM, MLC storage is hampered by noise and resistance drift. In this paper, the issue of reliability in MLC PCM is addressed. A statistical model is developed that captures the main impairments in MLC PCM cell-arrays. A signal processing and coding framework is then introduced that provides robustness to drift and noise, improving reliability and prolonging data retention. Several examples of codes are provided and practical detection schemes are described.

Investigation of Al-Sb-Se alloy for long data retention and low power consumption phase change memory application

Te-free phase-change material Al-Sb-Se is investigated and considered to be a promising candidate of storage medium for phase change memory (PCM) application. Al0.49Sb2.19Se exhibits a higher crystallization temperature (∼222.7 °C), a larger crystallization activation energy (∼4.17 eV), and a better data retention (∼146.5 °C for 10 yr) in comparison with those of Ge2Sb2Te5. The uniformity of material distribution for crystalline film improves the reliability of phase change memory. Al0.49Sb2.19Se-based memory cell significantly shows lower power consumption for SET/RESET reversible switching than that of Ge2Sb2Te5-based one. Furthermore, PCM based on Al0.49Sb2.19Se shows endurance up to 3.5 × 103 cycles with stability resistance of about two orders of magnitude on/off ratio.

Modeling Resistance Instabilities of Set and Reset States in Phase Change Memory With Ge-Rich GeSbTe

To satisfy the growing market demand for embedded nonvolatile memory, alternative solutions to Flash technology are currently under investigation. Among these, phase change memory (PCM) is attracting strong interest due to the low cost of integration with the CMOS front-end and good scalability. Embedded PCM, however, must feature high reliability during both packaging and functional stages. This paper studies reliability of PCM based on Ge-rich GeSbTe, providing evidence for resistance drift and decay in both the reset and set states. Set-state instability is attributed to grain-boundary relaxation and grain growth. A unified model is presented, capable of predicting the reliability of set/reset states at elevated temperature.

Thermomechanical Analysis on the Phase Stability of Nitrogen-Doped Amorphous Ge2Sb2Te5Films

The phase stability of amorphous Ge2Sb2Te5 (GST) films affects the performance and reliability of phase change memory (PRAM) devices. The viscosity and the glass forming ability of nitrogen (N)-doped amorphous GST films were investigated in terms of thermomechanical behavior using wafer curvature measurements. The viscosity which increased by two orders of magnitude was observed in the N-doped amorphous GST film by measuring the stress relaxation accompanied by bimolecular structural relaxation. The glass forming ability (ΔTx), difference between the glass transition temperature (Tg) and the crystallization temperature (Tc), of GST increased as the nitrogen contents increased. These increases in the viscosity and ΔTx indicate the retardation of atomic diffusion in amorphous GST and the stabilization of the amorphous phase.

Thermomechanical Analysis on the Phase Stability of Nitrogen-Doped Amorphous Ge2Sb2Te5 Films

The phase stability of amorphous Ge2Sb2Te5 (GST) films affects the performance and reliability of phase change memory (PRAM) devices. The viscosity and the glass forming ability of nitrogen (N)-doped amorphous GST films were investigated in terms of thermomechanical behavior using wafer curvature measurements. The viscosity which increased by two orders of magnitude was observed in the N-doped amorphous GST film by measuring the stress relaxation accompanied by bimolecular structural relaxation. The glass forming ability (ΔTx), difference between the glass transition temperature (Tg) and the crystallization temperature (Tc), of GST increased as the nitrogen contents increased. These increases in the viscosity and ΔTx indicate the retardation of atomic diffusion in amorphous GST and the stabilization of the amorphous phase.

Resistance and Threshold Switching Voltage Drift Behavior in Phase-Change Memory and Their Temperature Dependence at Microsecond Time Scales Studied Using a Micro-Thermal Stage

We study the drift behavior of RESET resistance RRESET and threshold switching voltage Vth in phase-change memory (PCM) and their temperature dependence. To extend the temperature-dependent measurement to microsecond time scales, we integrate an innovative micro-thermal stage (MTS) on the PCM cell. The MTS changes the temperature of the programmed region of the PCM cell within a few microseconds by placing the Pt heater in close proximity of the programmed region. First, we experimentally verify the existing phenomenological RRESET and Vth drift model for constant annealing temperature at various temperatures between 25°C and 185°C down to 100 μs and show that the measured temperature dependence of the drift coefficient agrees well with what is expected from the existing drift models. Based on the existing drift model for a constant annealing temperature, we derive the analytical expression for the RRESET drift for time-varying annealing temperature and experimentally verify the analytical expression. The derived analytical expression is important to understand the impact of thermal disturbance on PCM reliability such as variations in RRESET and Vth.

Phase Change Memory

In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Understanding Phase Change Memory Reliability and Scaling by Physical Models of the Amorphous Chalcogenide Phase

AbstractPhase change memory (PCM) devices are based on the electrically-induced change of phase within an active chalcogenide material. PCM features large resistance window, fast threshold/phase switching and high endurance, thus motivating a broad interest as potential Flash replacement and/or nonvolatile storage class memory. Despite the relatively mature progress of research and technology, there is still a wide debate about the ultimate scaling perspective for PCMs. Structural relaxation, crystallization and noise affecting the amorphous chalcogenide phase need to be addressed by accurate physical models for a realistic scaling projection. This work discusses the scaling of PCM devices in terms of the conduction mechanisms and structural stability of the amorphous chalcogenide phase. Resistance window narrowing, current fluctuations, resistance drift and crystallization in the amorphous phase will be explained by a unified model for thermal excitation of the structure by many-phonon phenomena. The downscaling of the reset current, needed to reduce the cell area in memory arrays, and thermal disturb between adjacent cells during reset will be finally addressed to assess the scaling capability of high-density PCM crossbar architectures.