RESET current optimization for phase change memory based on the sub-threshold slope

Abstract

The RESET current (Irst) is a key parameter to characterize power consumption and reliability of phase change memory (PCM) device. And the Optimization of Irst is a classic issue in the investigation of PCM targeting to meet various demands. In this paper, a RESET current optimization method, based on the relationship between the RESET current and the sub-threshold slope (STS), has been presented. Different from the conventional way which uses resistance values and bit yields, the new method that adopting the STS extracted from the V–I characteristics is simple, efficient and non-destructive. Here, the experimental results collected from sample cells of a PCM array confirm that the STS can be an important indicator for RESET current optimization. Furthermore, the voltage stress and endurance performance of the PCM devices operated by different RESET current are also measured, which further prove that the optimal RESET current determined by the new method is beneficial for both power consumption and reliability.