Reliable Memory Research Articles

Multivariate Transfer Passenger Flow Forecasting with Data Imputation by Joint Deep Learning and Matrix Factorization

Accurate forecasting of the future transfer passenger flow from historical data is essential for helping travelers to adjust their trips, optimal resource allocation and alleviating traffic congestion. However, current studies have mainly emphasized predicting traffic parameters for a single type of transport, while lacking research into transfer passenger flow influenced by multiple factors across different transport modes. Additionally, efficient traffic prediction relies on high-quality traffic data, yet data loss issues are inevitable but often ignored. To fill these gaps, we present for the first time a reliable joint long short-term memory with matrix factorization deep learning model (i.e., Joint-IF) for accurate imputation and forecasting of transfer passenger flow between metro and bus. This hybrid Joint-IF model uses a repair-before-prediction strategy to deliver the final high-quality outputs. In particular, we simulate a variety of missing combinations under the natural conditions and apply a low-rank matrix factorization to infer those lost values. In addition, we investigate the effects of crucial parameters and spatiotemporal features on transfer flow prediction. To validate the effectiveness of Joint-IF, a large series of experiments are carried out for models’ comparison and validation on the real-world transfer passenger flow dataset of the Shenzhen public transport system, and the results show that the proposed Joint-IF performs better for both imputation and forecasting of transfer passenger flow relative to the baseline models in terms of accuracy and stability.

Validity of Variable Message Sign Information: Is It Influenced by Drivers’ Short-Term Memory?

Variable message signs (VMSs), as a key component of intelligent transportation systems, have been frequently used in the management of urban roads to provide drivers with real-time traffic information. Nevertheless, a lack of unified regulations for VMS design, makes it difficult to accurately determine the validity of VMS information. In practice, inappropriately designed VMSs (e.g., VMSs overloaded with information and long setting distances) are common. In this study, laboratory simulation trials were conducted to assess VMS information validity in relation to the short-term memory (STM) capacity of drivers. Specifically, drivers capacity to easily obtain and respond correctly to valid VMS information based on memorized target information. Sixty participants completed the trials and pre-/postquestionnaires. Subjective evaluation, dynamic information acquisition rate, accuracy, and memory reliability were analyzed to evaluate their relationship with VMS information validity. The results confirmed that STM considering the information demand rate significantly affected the validity of the VMS information. Information validity deteriorated as the information volume and VMS setting distance increased. Reasonable validity was found when memory reliability ranged between 0.85 and 1.5 and the information volume was no more than 90 bits, corresponding to a subjective evaluation of 1, an accuracy of at least 80%, and a suggested STM time of 43.46 s. These criteria would satisfy driver information demand and prevent information redundancy or wasting of resources. These findings provide a basis for determining the thresholds for VMS information to promote practical and user-friendly VMS designs on urban roads.

Effect of Edge Roughness on Resistance and Switching Voltage of Magnetic Tunnel Junctions

We investigate the impact of edge roughness on the electrical transport properties of magnetic tunnel junctions using non-equilibrium Green’s function formalism. We have modeled edge roughness as a stochastic variation in the cross-sectional profile of magnetic tunnel junction characterized by the stretched exponential decay of the correlation function. The stochastic variation in the shape and size changes the transverse energy mode profile and gives rise to variations in the resistance and switching voltage of the magnetic tunnel junction. We find that the variations are larger as the magnetic tunnel junction size is scaled down due to the quantum confinement effect. A model is proposed for the efficient calculation of edge roughness effects by approximating the cross-sectional geometry to a circle with the same cross-sectional area. Further improvement can be obtained by approximating the cross-sectional area to an ellipse with an aspect ratio determined by the first transverse eigenvalue corresponding to the 2D cross-section. These results would be useful for designing reliable spin transfer torque-magnetic random access memory (STT-MRAM) with ultra-small magnetic tunnel junctions.

Driving and forgetting: Why what we remember isn’t what occured

It is a commonly held belief that our memories are good, that we can recall all the things that we saw and that happened to us. On our drive to or from work we can describe with confidence the route we took and what the traffic was like. But driving is very proceduralised, and our memory for what happened most recently is often based on what we usually see, a pastiche of events that may have happened, or not. This experiment set out to extend our understanding of memory reliability by testing people’s recollections about a recent drive. Over two drives participants traversed familiar roads in the University of Waikato driving simulator. Participants took three memory tests about what they saw during the drives. The first one was after a control drive, the second one after a drive in which the participant called out interesting, unusual, and hazardous objects (a detection task), and a third memory test was 48 h after completing the second drive. The results of the memory test showed a typicality effect, with drivers’ memories being almost twice as accurate for very atypical events they encountered. There was also a delayed recognition effect, with recall 48 h after experiencing lower rates of recognition than either immediate condition. The rates of false alarms were over 50% for the delayed recognition of very typical and medium items. Immediate memories of very typical items by the control group were also high (nearly 40%). The act of looking for something while driving (the detection task) had the effect of reducing the false alarm rate for all items. The rate of false alarms was very low for very atypical items under all tasks. The results are interpreted as being of importance for those interested in memory and attention, as a means of determining what drivers attend to, and what they do not.

Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation

Memory reliability is a critical issue in SRAM-based In-Memory Computing (IMC) architecture. The rapid advance in transistor technology makes SRAM more sensitive to soft errors. Various developments have recommended different methods to prevent store data corruption using Hamming Code. In order to encode or decode the information, a piece of Error Correction Code (ECC) hardware is necessary, which results in an area and energy overhead. In this paper, an IMC-based linear Error Correction Codec (IMC-ECC) hardware for parity check bit generation (encoding) and syndrome vector generation (decoding) is implemented by using the proposed Transmission Pass Gate (TPG) Local Bit-line (LB-8T) SRAM structure based IMC architecture. The local bit line structure resolves the half-select issues that occur for bit-interleave architecture. The TPG improves the write stability by delivering both strong VDD and GND. Furthermore, the proposed IMC-ECC scheme, along with bit-interleave architecture, makes the IMC architecture more resilient to multi-bit soft error. The proposed IMC-ECC scheme is validated by implementing a 4 Kb LB-8T SRAM array in 65 nm CMOS technology and Hamming code (7, 4) as an example. The proposed IMC-ECC scheme achieves the average energy consumption of 0.294 pJ/bit and 0.075 pJ/bit for the encoding and decoding process, respectively, at a supply voltage of 1 V.

Controllable coexistence of threshold and non-volatile crosspoint memory for highly linear synaptic device applications

A highly reliable and versatile resistive memory device that demonstrates threshold and non-volatile memory (NVM) switching behaviour depending on the compliance current (CC) modulation was utilised by doping a semiconducting (Si) material into a high-k (HfO x ) film with highly linear synaptic behaviour. The device shifted towards volatile switching at a CC less than 1 µA and exhibited NVM behaviour at a CC limit above 10 µA. A 3-bit/cell data storage capability on RESET voltage modulation was implemented for high-density memory application. The device exhibited excellent programming linearity of potentiation/depression responses up to 10 000 pulses compatible with fast pulse (100 ns) with good I ON/I OFF ratio (>103), stable data retention capability (105 s) at 85 °C and high WRITE endurance (∼107 cycles) with a pulse width of 200 ns. The neuromorphic applications were successfully emulated through neural network simulations using the experimentally calibrated data of the Si-doped HfO x resistive cross-point devices. Simulation results revealed a low nonlinearity of 0.03 with 98.08% pattern recognition accuracy. The estimated results revealed the potential of the device as a low-power selector and high-density NVM storage in large-scale crossbar array in future neuromorphic computing applications.

Stopping Voltage‐Dependent PCM and RRAM‐Based Neuromorphic Characteristics of Germanium Telluride

AbstractRecently, phase change chalcogenides, such as monochalcogenides, are reported as switching materials for conduction‐bridge‐based memristors. However, the switching mechanism focused on the formation and rupture of an Ag filament during the SET and RESET, neglecting the contributions of the phase change phenomenon and the distribution and re‐distribution of germanium vacancies defects. The different thicknesses of germanium telluride (GeTe)‐based Ag/GeTe/Pt devices are investigated and the effectiveness of phase loops and defect loops future application in neuromorphic computing are explored. GeTe‐based devices with thicknesses of 70, 100, and 200 nm, are fabricated and their electrical characteristics are investigated. Highly reproducible phase change and defect‐based characteristics for a 100 nm‐thick GeTe device are obtained. However, 70 and 200 nm‐thick devices are unfavorable for the reliable memory characteristics. Upon further analysis of the Ag/GeTe/Pt device with 100 nm of GeTe, it is discovered that a state‐of‐the‐art dependency of phase loops and defect loops exists on the starting and stopping voltage sweeps applied on the top Ag electrode. These findings allow for a deeper understanding of the switching mechanism of monochalcogenide‐based conduction‐bridge memristors.

Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics

3D flash memories have been widely developed to further increase the storage capacity of SSDs by vertically stacking multiple layers. However, this special physical structure brings new error characteristics. Existing studies have discovered that there exist significant Raw Bit Error Rate (RBER) variations among different layers and RBER similarity inside the same layer due to the manufacturing process. These error characteristics would introduce a new data reliability issue. Currently, Low-Density Parity-Check (LDPC) code has been widely used to ensure the data reliability of flash memories. It can provide stronger error correction capability for high RBERs by trading with longer read latency. Traditional LDPC codes designed for planar flash memories do not consider the layer RBER characteristics of 3D flash memories, which may induce sub-optimal read performance. This article first investigates the effect of RBER characteristics of 3D flash memories on read performance and then obtains two observations. On one hand, we observe that LDPC read latencies are largely diverse in different flash layers and increase in diverse speeds along with data retention. This phenomenon is caused by the inter-layer RBER variation. On the other hand, we also compare RBERs between different pages of the same flash layer and observe that read latencies with LDPC codes are quite similar, which is caused by the intra-layer RBER similarity. Then, by exploiting these two observation results, this article proposes a Multi-Granularity LDPC (MG-LDPC) read method to adapt read latency increase characteristics across 3D flash layers. In detail, we design five LDPC decoding engines with varied read level increase granularity (higher level induces higher latency) and assign these engines to each layer dynamically according to prior information, or in a fixed way. A series of experimental results demonstrate that the fixed and dynamic MG-LDPC methods can reduce SSD read response time by 21% and 51% on average, respectively.

Room‐Temperature‐Processable Highly Reliable Resistive Switching Memory with Reconfigurability for Neuromorphic Computing and Ultrasonic Tissue Classification (Adv. Funct. Mater. 14/2023)

Resistive Switching Memory In article number 2213064, Hui Joon Park, Jong Hwan Ko, Daeho Lee, and co-workers demonstrate analog resistive switching memory (RSM) with unprecedentedly high reliability and robustness by laser-assisted photo-thermochemical process. This is compatible with back-end-of-line process and flexible format. With its superior characteristics, practical adaptive learning rule is designed and applied to ultrasonic tissue-classification task with high computing accuracy. This RSM also has reconfigurability working as a diffusive-memristor.

Switchable Polar Nanotexture in Nanolaminates HfO2 -ZrO2 for Ultrafast Logic-in-Memory Operations.

Nontrivial topological polar textures in ferroelectric materials, including vortices, skyrmions, and others, have the potential to develop ultrafast, high-density, reliable multilevel memory storage and conceptually innovative processing units, even beyond the limit of binary storage of 180° aligned polar materials. However, the realization of switchable polar textures at room temperature in ferroelectric materials integrated directly into silicon using a straightforward large area fabrication technique and effectively utilizing it to design multilevel programable memory and processing units has not yet been demonstrated. Here, utilizing vector piezoresponse force and conductive atomic force microscopy, microscopic evidence of the electric field switchable polar nanotexture is provided at room temperature in HfO2 -ZrO2 nanolaminates grown directly onto silicon using an atomic layer deposition technique. Additionally, a two-terminal Au/nanolaminates/Si ferroelectric tunnel junction is designed, which shows ultrafast (≈83ns) nonvolatile multilevel current switching with high on/off ratio (>106 ), long-term durability (>4000 s), and giant tunnel electroresistance (108 %). Furthermore, 14 Boolean logic operations are tested utilizing a single device as a proof-of-concept for reconfigurable logic-in-memory processing. The results offer a potential approach to "processing with polar textures" and addressing the challenges of developing high-performance multilevel in-memory processing technology by virtue of its fundamentally distinct mechanism of operation.

Superior resistive switching performance in SnO2 nanoparticles embedded TiO2 nanorods-based thin films

Resistive random-access memories are ideal candidates for next-generation non-volatile memories due to their simple structure, fast response, and low power consumption. One-dimensional nanostructured memories are of particular importance owing to their electron transport confinement in individual components (such as nanorods/nanowires) that can provide extra control to finely tune the electrical performance for stable and reliable memory operations. In this work, vertically oriented one-dimensional TiO2 nanorods were fabricated via a simple and facile solvothermal technique. Besides, SnO2 nanoparticles were embedded on TiO2 nanorods matrix (to form a nanocomposite) and their resistive switching characteristics were evaluated and compared. Although, both devices expressed good resistive switching behavior. However, the nanocomposite device showed superior switching performance than the control (TiO2 nanorods) one. Moreover, the nanocomposite device demonstrated additional features of multilevel data storage and the prediction of switching probabilities at lower potentials to be applied in neuromorphic computing. The governing resistive switching mechanism was explored, and the role of oxygen vacancies was identified as critical for the switching and charge transport mechanism in the investigated devices.

Slovenian Version of the Deese–Roediger–McDermott Paradigm: A Normative and Exploratory Study

The research with the Deese–Roediger–McDermott (DRM) paradigm has accumulated substantial evidence for the reliable cross-cultural false memory effect. However, only a limited set of languages has had the benefit of receiving their own version of the DRM paradigm, let alone the corresponding normative data. In this study, we used 728 participants (594 women) to create the first Slovenian version of the DRM paradigm, and another 90 participants (66 women) to test its effectiveness in inducing false memories and conduct exploratory analyses. We are the first one to conduct a normative DRM study entirely online and among the few that measured reaction times (RTs) besides commonly employed accuracy measures. Overall, the participants recalled 69% of the list items and 14% of the critical lures, and additionally recognised 79% of the list items and 45% of the critical lures. The participants recalled and recognised list items as fast as critical lures and significantly faster than unrelated words. The study shows that false memories can be effectively explored by using the online format of the DRM paradigm. Future studies should investigate the relationship between RTs and accuracy measures, the relationship between recall and recognition, as well as the effects of the experimental environment on the results of the DRM studies in more detail. We hope that the provided material and its scrutiny will contribute to the progress in false memory research, especially in the Slovenian language environment.

Characterization of a novel radiation hardened by design (RHD14) bit-cell based on 20-nm FinFET technology using TCAD simulations

Radiation has been a traditional concern in microelectronic devices used in space applications, causing high probability of single event upsets (SEUs). SEUs induced by particle radiation are becoming an increasingly important threat to the reliability of memories. Moreover, recent studies reveals that single event multiple-node upsets (SEMNUs) is the prime effect of radiation in SRAM chips fabricated in nanoscale CMOS technologies. In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed in this paper to address the issues related to SEUs and SEMNUs. Hardness against radiation of the proposed bit-cell is compared with the recently reported radiation hardened bit-cells and popular SRAM bit-cell (6T). Radiation and its effect in the bit-cells under consideration are simulated with the help of 3-D Technology Computer Aided Design (TCAD) and Visual Particle (VP) tools. Radiation hardening capability of RHD14 over the existing and conventional bit-cells is demonstrated focusing on linear energy transfer (LET) threshold and recovery time. It is observed that the proposed radiation hardened cell needs lesser silicon area and performs better in terms of power dissipation. Other performance metrics like read delay, write delay are also evaluated in order to study ensuing trade-off.

Exploiting Metadata to Estimate Read Reference Voltage for 3-D nand Flash Memory

In consumer electronics, 3-D NAND flash memory has become the state-of-the-art storage medium due to the multi-bit storage per cell and 3-D stacking technology. However, flash memory cells are commonly vulnerable to numerous types of circuit-level noise, resulting in threshold voltage distribution distortion and decreased reliability. Characterization of the threshold voltage distribution and modeling of optimal read reference voltages can help to mitigate the reliability deterioration. We provide a solution for improving the reliability of flash memories while reducing their implementation cost in this paper. The proposed pre-processing method is shown to yield a smaller number of scanning voltage steps reducing the time overhead and energy consumption of multiple read operations during the characterization of threshold voltage distributions. We propose a single state asynchronous estimation (SSAE) method to estimate optimal read reference voltages. Compared with the advanced two-state asynchronous estimation (TSAE) method, it is shown to reduce the computational and space overhead by half. Furthermore, compared with using the default read reference voltages, it is also shown to reduce RBER without exact knowledge of noise.

Room‐Temperature‐Processable Highly Reliable Resistive Switching Memory with Reconfigurability for Neuromorphic Computing and Ultrasonic Tissue Classification

AbstractReversible metal‐filamentary mechanism has been widely investigated to design an analog resistive switching memory (RSM) for neuromorphic hardware‐implementation. However, uncontrollable filament‐formation, inducing its reliability issues, has been a fundamental challenge. Here, an analog RSM with 3D ion transport channels that can provide unprecedentedly high reliability and robustness is demonstrated. This architecture is realized by a laser‐assisted photo‐thermochemical process, compatible with the back‐end‐of‐line process and even applicable to a flexible format. These superior characteristics also lead to the proposal of a practical adaptive learning rule for hardware neural networks that can significantly simplify the voltage pulse application methodology even with high computing accuracy. A neural network, which can perform the biological tissue classification task using the ultrasound signals, is designed, and the simulation results confirm that this practical adaptive learning rule is efficient enough to classify these weak and complicated signals with high accuracy (97%). Furthermore, the proposed RSM can work as a diffusive‐memristor at the opposite voltage polarity, exhibiting extremely stable threshold switching characteristics. In this mode, several crucial operations in biological nervous systems, such as Ca2+ dynamics and nonlinear integrate‐and‐fire functions of neurons, are successfully emulated. This reconfigurability is also exceedingly beneficial for decreasing the complexity of systems—requiring both drift‐ and diffusive‐memristors.

WiSE: When Learning Assists Resolving STT-MRAM Efficiency Challenges

Spin Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising on-chip technologies, which delivers high density, non-volatility, and near-zero leakage power. However, Spin Transfer Torque Magnetic RAM (STT-MRAM) suffers from three reliability issues, namely, read disturbance, write failure, and retention failure, that present significant challenges to its use as a reliable on-chip memory. All of these three reliability challenges become even more threatening with any increase in STT-MRAM cell temperature. Write operations are regarded as the main source of heat generation and temperature increase in STT-MRAM on-chip memories. This article first presents experiments to show how the heat generated by consecutive writes affects the reliability of an STT-MRAM on-chip cache. Then, it proposes the WiSE framework, an approach to reduce the STT-MRAM-based cache memory temperature and improve its reliability. WiSE utilizes the Reinforcement Learning (Reinforcement Learning (RL)) technique to detect high-density write operation patterns in STT-MRAM cache. To manage the write operations across the STT-MRAM caches, WiSE introduces a new temperature-aware replacement policy. The simulation results show that while WiSE imposes only about 1% performance overhead, it improves retention failure rate, read disturbance rate and write failure rate by 64%, 57%, and 47%, respectively, compared to Least Recently Used (Least Recently Used (LRU)) replacement policy.

Relationships between Age, Subjective Memory, Metacognition and Thought-Action Fusion

It is unclear how the relationships between age and metacognitive beliefs are affected by beliefs about memory. To examine this question, we measured beliefs about memory (reliability of memory and retrospective changes in memory), metacognitive beliefs (using the Metacognitions Questionnaire-30 [MCQ-30]) and Thought-Action Fusion (TAF) in a large sample of participants (n = 812) over a wide age range (17-64 years) using a cross-sectional design. Participants who reported positive beliefs regarding memory reliability and retrospective changes in memory had more positive MCQ-30 scores.

SAM: A Mechanism to Facilitate Smear-Aware Forensic Analysis of Volatile System Memory

Page smear is a phenomenon that occurs when a system’s volatile memory dump is obtained in a non-atomic manner; it’s more common in systems with a lot of RAM and different workloads. It has a considerable impact on the quality and reliability of the forensic artifacts obtained, as well as the analysis of such snapshots. We present SAM, a timeline-based page table state information collection mechanism that enables a reliable memory analysis. It facilitates visualizing inconsistencies in the page table data structure and provides the investigator with a reliable source of page table information to deal with the inconsistent values.

Performance enhancement of on-chip optical switch and memory using Ge2Sb2Te5 slot-assisted microring resonator

Phase change material Ge2Sb2Te5 (GST) has recently emerged as a highly promising candidate for reconfigurable photonic devices owing to its non-volatility, high optical contrast, and fast transition speed between the amorphous and crystalline states. We propose a novel nonvolatile 1 × 2 optical switching and multi-level memory based on a GST slot-assisted microring resonator (MRR). GST slot is embedded in silicon microring resonator to enhance the light-matter interaction. The device demonstrates a low insertion loss of 0.7 dB in the amorphous state at the drop port and 0.1 dB in the crystalline state at the through port. The high extinction ratios of around 28.32 dB and 22.71 dB can be achieved at the drop and through ports, respectively. A multi-level photonic memory was proposed by combining MRR and a U-bend feedback loop embedded with GST slot. Free spectral range can be expanded from 21.6 nm to 43.2 nm by modifying the length of the feedback loop instead of the microring diameter. The minimum read contrast of 19% among each level can be achieved by changing two GST states individually for a reliable 4-level memory. The 2-level memory demonstrates a read contrast of 90% which is around 4.3 times higher than the traditional device. Our all-optical approach represents a significant step towards the development of low-loss and reliable photonic memory for neuromorphic computing and artificial intelligence.

Memory Sins in Applied Settings: What Kind of Progress?

Over two decades ago, I proposed that memory errors could be classified into seven basic categories or sins (Schacter, 1999, 2001), comprising three sins of omission (transience, absentmindedness, and blocking) and four sins of commission (misattribution, suggestibility, bias, and persistence). In the past two decades, much has been learned about the nature and basis of the memory sins. Here, I assess the extent of progress that has been made during that time regarding applied implications of five of the sins: transience, absentmindedness, misattribution, suggestibility, and persistence. The manifestations of these sins have been examined in a variety of applied settings, including educational, clinical, legal, and technological domains. I argue that considerable progress has been made in characterizing the impact of memory sins in each domain, identify gaps in and limitations of our current knowledge, and briefly consider how these developments bear on broad questions regarding the reliability of human memory.