Relaxed Silicon Germanium Research Articles

Laser‐Annealed SiO2/Si1−xGex Scaffolds for Nanoscaled Devices, Synergy of Experiment, and Computation

Laser‐Annealed SiO₂/Si_1−<i>x</i>Ge_<i>x</i> Scaffolds for Nanoscaled Devices, Synergy of Experiment, and Computation

New Strategies for Engineering Tensile Strained Si Layers for Novel n-Type MOSFET

We report a novel approach for engineering tensely strained Si layers on a relaxed silicon germanium on insulator (SGOI) film using a combination of condensation, annealing, and epitaxy in conditions specifically chosen from elastic simulations. The study shows the remarkable role of the SiO2 buried oxide layer (BOX) on the elastic behavior of the system. We show that tensely strained Si can be engineered by using alternatively rigidity (at low temperature) and viscoelasticity (at high temperature) of the SiO2 substrate. In these conditions, we get a Si strained layer perfectly flat and free of defects on top of relaxed Si1-xGex. We found very specific annealing conditions to relax SGOI while keeping a homogeneous Ge concentration and an excellent thickness uniformity resulting from the viscoelasticity of SiO2 at this temperature, which would allow layer-by-layer matter redistribution. Remarkably, the Si layer epitaxially grown on relaxed SGOI remains fully strained with -0.85% tensile strain. The absence of strain sharing (between Si1-xGex and Si) is explained by the rigidity of the Si1-xGex/BOX interface at low temperature. Elastic simulations of the real system show that, because of the very specific elastic characteristics of SiO2, there are unique experimental conditions that both relax Si1-xGex and keep Si strained. Various epitaxial processes could be revisited in light of these new results. The generic and simple process implemented here meets all the requirements of the microelectronics industry and should be rapidly integrated in the fabrication lines of large multifinger 2.5 V n-type MOSFET on SOI used for RF-switch applications and for many other applications.

Strained SI/SIGE/SI Nano-Channel Hoi Mosfet

Strained Si technology has headed in the development of single or dual channel strained silicon MOSFETs devices. Comprehending the need of advancement in recent technologies with miniaturized features, developing a novel MOSFET on ultrathin double strained Si with strained SiGe sandwiched in between and forming a tri-channel MOSFET has been the crux of this present research. Incorporation of quantum carrier confinement effect on the ultrathin dual strained Si layers in the channel has been implemented to counterbalance the threshold voltage roll-off induced by the strained layers. A comparison of the conventional strained silicon on relaxed silicon-germanium with double strained silicon channel MOSFET has been perceived leading to eloquent drain current enhancement of ~49% with a small reduction in the threshold voltage caused by the additional bottom strained Si layer. Further, 100nm and 50nm channel length have been compared and a superior device characteristic for the reduced device dimension is attained as the prominence of velocity overshoot is more in short channel device approaching to quasi-ballistic transport in the channel region

Reliability studies on biaxially tensile strained-Si channel p-MOSFETs

An integrated technology computer aided simulation framework is used for the first time to predict the reliability (degradation) of substrate-induced strained-Si channel heterojunction field effect transistors on relaxed Silicon-Germanium buffer layer with ultra-thin SiO2 and high-k gate stacks. State-of-the-art four-state nonradiative multiphonon model is used for the degradation studies. Single defects and trap studies have been taken up on devices subjected to negative voltage stressing at an elevated temperature. Threshold voltage shift (due to charge capture and emission processes) in virtually fabricated devices has been studied in detail. For the first time, non radiative multiphonon model is used to explain the degradation mechanisms (oxide defects dominating the partial recovery of threshold voltage after stressing) in strained-Si channel heterojunction field effect transistors. It is shown that degradation in strained-Si channel device on relaxed-SiGe buffer is more compared to its Si-channel counterpart.

Effect of Si/Sige Buried Gate with Strained Layers on N-Type Channel Properties

As the scaling down limit is approaching, the effect of structural and material specific limitations on the device characteristics was significantly increased. In terms of structure, formation of parasitic capacitors in the word line must be restricted in order to secure the sensing margin of the DRAM and the channel length must be secured for effective channel control. The buried gate is currently being applied in these two aspects. In terms of channel materials, as one of the possible candidates for mass-production, it is permissible to form strained silicon on the fully relaxed SiGe layer to improve the electron mobility. However, when growing SiGe without gradually increasing the concentration of Ge on Silicon substrate, the threading dislocation occur due to the lattice mismatch between the silicon substrate and silicon germanium layer. In this study, the process were investigated to form defect free and fully relaxed SiGe layer on silicon substrates by using hydrogen implantation and then growing strained silicon on the SiGe layer. The buried gate formed from the strained silicon surface to the top of the relaxed silicon germanium layer and the effect of strained Si and SiGe n-type channel characteristics on the device was investigated. We present a review on defect-free SiGe layer formation and device characteristics including the electron mobility of the strained Si/SiGe buried gate.

High-resolution x-ray reflection Fourier analysis of metamorphic Si/SiGe quantum wells

Graded buffer metamorphic epitaxial heterostructures are extraordinarily difficult to analyze using x-ray diffraction because of large signal contributions from the buffer. As an alternative, Fourier signal processing is applied to x-ray reflectivity data such that layer thickness and reflectivity strength are readily extracted. This analysis is applied to two strained silicon quantum wells grown inside relaxed silicon germanium barriers. Analysis of the x-ray reflectivity data directly determines that the quantum wells are 8.5 and 8.7 nm spaced by a 22.0-nm thick barrier. These values agree with those extracted from transmission electron microscopy to better than 0.5 nm.

Group IV heteroepitaxy on silicon for photonics

Abstract

Strain Relaxed Silicon Germanium Buffer Layers: From Growth to Integration Challenges

Silicon germanium (SiGe) strain relaxed buffers (SRB) have been an active area of investigation both in academia as well as the semiconductor industry for a number of years [1, 2]. These relaxed epitaxial layers act as virtual substrates or templates for subsequent growth of tensile or compressively strained layers that can serve as N and PMOS channels for continued scaling of Si CMOS technology. The most well established methodology, proposed by Fitzgerald et al. [1], for growing SiGe SRB’s is by grading the Ge concentration throughout the layer, typically 2-3 µm thick, which leads to the creation of a series of low lattice mismatched interfaces. By managing the lattice mismatch using this grading method the threading dislocation density (TDD) can be reduced significantly. In the work reported here, we have studied thick graded SRB layers from a holistic perspective that involves growth, defect density optimization followed by the growth of strained Si/SiGe layers on these virtual substrates. The focus during this study was on the high temperature growth regime (> 900 oC) which helps reduce TDD due to the higher dislocation velocity resulting in a higher number of dislocation annihilation events. Depicted in Fig. 1 is one such example, where a 2 µm graded layer (0-20 % Ge grading) was grown followed by a 1 µm layer at 20 % Ge analyzed using SIMS. The growth for this sample was carried out using Dichlorosilane (SiH2Cl2 or DCS) and Germane (GeH4) at 900 oC and 80 Torr under H2 ambient in an Applied Materials CenturaTM RP Epi reactor. From a morphology perspective these films are extremely rough after growth due to the well-known cross hatch pattern formation as shown in the AFM scan in Fig. 2 (a). In order to enable growth of strained and atomically smooth channel layers on top of this SRB, a chemical-mechanical planarization (CMP) step is required to remove the cross-hatch and leave behind a much smoother template. As shown in Fig. 2(b), Applied Materials ReflexionTM LK CMP tool was able to polish these substrates down to an RMS roughness of ~ 1.3 Å, compared to a starting RMS roughness of ~ 66 Å, after ~ 0.2 µm removal of the 20 % Ge constant composition layer. To characterize the TDD for this layer, plan view transmission electron microscopy (PV-TEM) was performed and the results are shown in Fig. 3. As seen in this case, 2 threading dislocations are visible in a 100 µm2 area which translates to a TDD of ~ 2 x 10 6 /cm2. PV-TEM however, has limited resolution and led us to explore large area defect etching utilizing vapor phase hydrochloric acid (HCl) in the epi reactor itself [3]. HCl based defect etching was done on SRB samples grown at various temperatures in the 900 – 1100 oC range after they had gone through CMP. The resulting etch pits, which in essence are highlighted threading dislocations, were inspected optically on a 300 µm2 area as shown in Table 1 where 1100 oC growth resulted in the lowest TDD ~ 5 x 10 4 /cm2. For temperatures greater than 1000 oC, GeCl4 was used instead of GeH4 in order to keep the process chamber walls clean. Another critical aspect of SRB integration is the growth of strained Si or SiGe layers on top of this relaxed layer. These strained layers serve as the channel material for N or PMOS transistors. Figure 4 represents one such illustration in the form of a cross-section TEM where we have grown a Si layer under tensile strain, 436 Å in thickness, on a 30 % Ge graded SRB layer post CMP. This Si layer appears to be defect free, and based on the (224) reciprocal space map (RSM: In Fig. 5) acquired using X-ray diffraction techniques, it is < 5 % relaxed with respect to the underlying SRB. A systematic optimization of epi pre-clean and H2 pre-bake had to be performed to achieve defect free Si or SiGe (~ 60-70 % Ge) growth on SRB templates. In summary, we have explored the growth and integration of SiGe SRB layers in order to enable scaling for future generation CMOS technology beyond 7 nm. Higher growth temperatures (> 1000 oC) were effective in improving the TDD by almost two orders of magnitude. Pseudomorphically strained N and P channel growth on SiGe SRB has also been achieved by optimizing the pre-clean and prebake conditions.

Strain Relaxed Silicon Germanium Buffer Layers: From Growth to Integration Challenges

Silicon Germanium (SiGe) strain relaxed buffers (SRB) are fully relaxed epitaxial layers that serve as templates for subsequent growth of tensile or compressively strained layers that can serve as N and P channels for continued scaling of Si CMOS technology. In the work reported here, we have studied thick graded SRB layers from a holistic perspective which includes SRB growth targeting defect density optimization followed by the growth of strained Si/SiGe layers on these virtual substrates.

Etch Pit Formation on Germanium Alloys by in situ Gaseous Hydrogen Chloride Etching

Etch pits form on epitaxial germanium alloy surfaces after in situ gaseous hydrogen chloride etching. The etch pits on the (001) surfaces of germanium, germanium-rich silicon germanium, and germanium tin are shown to be correlated with the threading dislocations in these epitaxial films. The etch pits therefore offer a direct way to characterize the distribution and density of threading dislocations in germanium alloys. Etch pits on strained and relaxed silicon germanium and germanium tin films are compared.

(Invited) Fabrication of High-Quality GOI and SGOI Structures by Rapid Melt Growth Method - Novel Platform for High-Mobility Transistors and Photonic Devices -

High-quality germanium-on-insulator (GOI) and fully relaxed silicon germanium(SiGe)-on-insulator (SGOI) structures have been demonstrated by the rapid melt growth method. We successfully fabricated single-crystalline local GOI structures, that is, Ge wires over 100 um long within microcrucibles of a few um wide by means of lateral liquid phase epitaxy (lateral LPE). GOI MOSFETs produced by lateral LPE exhibited superior carrier mobility and on/off current ratio to those of conventional SOI devices, indicating excellent electrical properties of Ge-channel and MOS interface formed by LPE. Moreover, dislocation-free fully relaxed SiGe layers on SOI substrates were demonstrated by vertical LPE, in which crystallographic defects were found to be confined within the compositionally graded SiGe interlayer between the epitaxcially grown relaxed SiGe and SOI layers. These novel methods based on the rapid metal growth will open up a new pathway to realize platform for next-generation Ge-based high-mobility transistors and photonic devices.

Fabrication of Strain Relaxed Silicon-Germanium-on-Insulator (Si0.35Ge0.65OI) Wafers using Cyclical Thermal Oxidation and Annealing

AbstractA novel scheme for the fabrication of SiGe-on-insulator (SGOI) substrates comprising a thin and relaxed silicon-germanium (SiGe) layer with high Ge mole fraction is reported. A cyclical thermal oxidation and annealing (CTOA) process is introduced to alleviate issues associated with surface roughening and non-uniformity in Ge content. A systematic study of the stress developed in the SiGe layer as condensation takes place is presented. A clear understanding of the strain evolution enables the SGOI substrate fabrication to be tailored according to the requirements of strain engineering in high mobility MOSFETs.

Maximizing uniaxial tensile strain in large-area silicon-on-insulator islands on compliant substrates

Recently we have demonstrated a process for generating uniaxial tensile strain in silicon. In this work, we generate uniaxially strained silicon and anisotropically strained silicon germanium on insulator with strain in both ⟨100⟩ and ⟨110⟩ in-plane directions. The strain is uniform over fairly large areas, and relaxed silicon-germanium alloy buffers are not used. The magnitude of uniaxial strain generated by the process is very dependent on the in-plane crystal direction, and can be modeled accurately using the known mechanical properties of silicon and germanium. A maximum uniaxial silicon strain of 1.0% in the ⟨100⟩ direction is achieved. Numerical simulations of the dynamic strain generation process are used to identify process windows for achieving maximum uniaxial silicon strain for different structural geometries.

Band-edge alignment ofSiGe∕Siquantum wells andSiGe∕Siself-assembled islands

We report on the energy band gap and band lineup of $\mathrm{SiGe}∕\mathrm{Si}$ heterostructures either in the case of coherently strained quantum wells or in the case of $\mathrm{SiGe}∕\mathrm{Si}$ self-assembled islands. We take into account the strain field and the quantum confinement effects through an accurate description of the conduction band including the $\ensuremath{\Delta}$ and $L$ bands. The strain field is calculated using a microscopic valence force field theory. The conduction-band diagram and energies are obtained from a 30-band $\mathbf{k}∙\mathbf{p}$ Hamiltonian accounting for the strain through the Bir-Pikus Hamiltonian. The band-edge description is first given for biaxially strained pseudomorphic $\mathrm{SiGe}$ layers. In $\mathrm{SiGe}$ quantum wells grown on relaxed silicon, the band line-up switches from type I to type II depending on the value of the average valence band offset. Applying the 30-band formalism to the case of heterostructures grown on relaxed silicon germanium buffer layers indicates that a better agreement with experimental data is obtained for a valence-band offset value $\mathrm{\ensuremath{\Delta}}{E}_{v}=0.54x$ where $x$ is the Ge composition. For this parameter, a type-II band lineup is thus expected for all compositions of pseudomorphic $\mathrm{SiGe}$/relaxed Si heterostructures. For $\mathrm{GeSi}∕\mathrm{Si}$ islands, we take into account the strain relaxation in the surrounding Si matrix. A type-II band lineup is predicted for all Ge compositions. The near-infrared interband recombination energy of the islands is calculated as a function of their $\mathrm{SiGe}$ composition.

Direct regrowth of thin strained silicon films on planarized relaxed silicon–germanium virtual substrates

We discuss a method for fabricating strained Si layers via deposition directly onto planarized relaxed SiGe virtual substrates, a process termed direct regrowth (DRG). We show that a trade-off exists between surface roughness and cleanliness of the Si/SiGe interface. Using this knowledge, we discuss process requirements to ensure that strained Si wafers produced via direct regrowth are free of interfacial contamination, exhibit ultra-low surface roughness, and feature abrupt Si/SiGe interfacial transitions. Finally, we show that metal-oxide-semiconductor field-effect transistors produced on strained Si channels fabricated via direct regrowth exhibit excellent device performance, suggesting the viability of the DRG process for manufacture of high quality strained Si wafers.

Extraction of strained-Si metal-oxide-semiconductor field-effect transistor parameters using small signal channel conductance method

Channel conductance has been employed to extract several important parameters such as threshold voltage, gain, effective channel length, series resistance, and mobility for strained-Si metal-oxide-semiconductor field-effect-transistors fabricated on relaxed silicon-germanium virtual substrates with Ge composition up to 25%. Analytical models have been developed by taking into account the effect of strain (i.e., Ge composition) on these parameters. The low field mobility of the devices has been found to increase linearly up to a Ge composition of 25% in the virtual substrate. A modified channel conductance technique has been used to extract critical fields accurately. This has also been used to predict the dependence of mobility on electric field in a strained-Si device. The critical field for silicon devices has been found to be 65kVcm−1, while for strained-Si devices, it has been found to decrease from 62.5 to 30kVcm−1 with increasing Ge composition (15% to 25%) in the virtual substrate. The reported results are useful for the design and simulation of strained-Si devices.

Germanium-concentration dependence of arsenic diffusion in silicon germanium alloys

The germanium-concentration dependence of arsenic diffusion in relaxed silicon germanium (Si1−xGex) alloys with Ge content ranging from 0 to 40% has been investigated. Arsenic was implanted into relaxed epitaxial layers at 15 keV to a dose of 3×1015 cm−2, and diffusion during furnace and rapid thermal annealing was studied. Under equilibrium extrinsic conditions, the arsenic diffusivity increases exponentially with increasing Ge content in Si1−xGex. Under transient diffusion conditions, the arsenic diffusivity in Si1−xGex is retarded compared to the diffusivity for longer times, while a slight transient enhancement of As diffusion is observed in Si. The degree of transient retardation depends on the germanium concentration in the alloy.

Impact of Ge diffusion and wafer cross hatching on strained Si MOSFET electrical parameters

ABSTRACTA contender for future generations of CMOS technology is the strained silicon (S-Si) MOSFET. The mobility enhancement in S-Si can be exploited to maintain the performance enhancements demanded by Moore's law with reduced critical dimensions. S-Si is obtained by growth of a thin Si layer over a thick virtual substrate (VS) of relaxed silicon-germanium (SiGe). The mobility of a surface channel MOSFET is dependent on the quality of the silicon-oxide (Si/SiO2) interface. Ge may out diffuse from the virtual substrate to the oxide interface causing an increase in trapping density. As the Ge content in the virtual substrate increases surface roughness also increases. These phenomena both lead to a reduction in mobility.The study of a matrix of devices having variable Ge composition and S-Si thickness is crucial in deconvolving the contributions of Ge diffusion and wafer cross-hatching roughness on electrical parameters. Increasing VS Ge composition increases the Ge concentration at the SSi/SiO2 interface and cross-hatching amplitude whereas reducing S-Si channel thickness only increases Ge concentration at the S-Si/SiO2 interface and does not increase cross-hatch amplitude. Interface state density, drive current, gate leakage current, transconductance and carrier mobility data are presented for this two-dimensional space of VS composition and S-Si thickness. The relative importance of Ge diffusion and cross-hatching roughness can be seen in this data. The results of this study indicate a lower limit of 7 nm for the S-Si thickness and an upper limit of approximately 20 % Ge in the virtual substrate for the current processing technology. Understanding the performance-limiting mechanisms in S-Si is crucial in the optimisation of VS Ge composition and S-Si thickness for current and future generations of S-Si CMOS.

Relaxed silicon-germanium on insulator substrate by layer transfer

The fabrication of 4 in, relaxed Si1−xGex-on-insulator (SGOI) substrates by layer transfer was demonstrated. A high-quality relaxed Si1−xGex layer was grown using ultrahigh vacuum chemical vapor deposition (UHVCVD) on 4 in. Si donor wafers. Thin Si−xGex film (x=0.2 or 0.25) was then transferred onto an oxidized Si handle wafer by bonding and wafer splitting using hydrogen implantation. The resulting relaxed SGOI structures were characterized by transmission electron microscopy (TEM) and atomic force microscopy (AFM).

Inter-edge-mode scattering in a high-mobility strained silicon two-dimensional electron system

The magnetoresistances of two-dimensional electron systems in strained silicon on a relaxed silicon-germanium buffer have been measured at low temperatures (50 mK). Samples, with Hall mobilities up to 3.61 × 105 cm2 V-1 s-1, have shown a marked asymmetry between adjacent Shubnikov-de Haas peaks and a prominent overshoot on the low-field side of the odd-filling-factor quantum Hall plateaux. This effect persisted to unusually small magnetic fields. It is argued that both of these phenomena can be explained by a strong back-scattering of multiple edge modes which is suppressed at integer filling factors.