Relaxed SiGe Layers Research Articles

Impact of thermal annealing on deep-level defects in strained-Si∕SiGe heterostructure

Si ∕ Si 1 − x Ge x ∕ Si heterostructures consisting of relaxed SiGe layers of graded and constant (x=0.2) composition with a strained-Si layer on top have been studied by the capacitance-voltage (C-V), deep-level transient spectroscopy (DLTS), and electron-beam induced current (EBIC) techniques. Analysis of the C-V and EBIC data shows that electrically active defects are introduced during growth into both the graded and constant-composition SiGe layers in a high concentration (∼1016cm−3). The defects are attributed to dislocation trails, i.e., the quasi-two-dimensional extended defects formed behind gliding threading dislocations. Electrical activity of the dislocation trails is reduced following the annealing at 800°C. The DLTS measurements reveal a much lower density of deep-level defects which are mainly located in the graded SiGe layer. The 800°C annealing also gives rise to an additional DLTS peak. The deep-level centers corresponding to this peak are located close to the strained-Si∕SiGe interface and can be attributed to partial relaxation of the strained-Si layer.

Condensation Mechanism for the Formation of Relaxed SiGe Layer Grown-on-Insulator

ABSTRACTThe condensation method to grow a strained SiGe layer-on-insulator (ε-SGOI) has attracted interests for the application of high speed complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) because of high quality properties and effective process cost. Although many reports presented its superiority in a device performance to bonding and dislocation sink technologies, the mechanism by which the condensation method produces ε-SGOI has also not been clearly explained and the surface properties have not been evaluated. Thus, we investigated condensation mechanism in detail by characterizing a surface property and Ge profile in SiGe layer. For the experiment, first, a SiGe layer on silicon-on-insulator layer was epitaxally grown at 550 °C, and three different oxidation thicknesses were grown at 950 °C, i.e., 40, 60, 90 nm. From our investigation results, we found that there are three steps in producing ε-SGOI. For the first step, by the 40-nm-thick oxidation, a diffusion of Ge atoms in SiGe layer into Si layer-on-insulator was generated and Ge atoms were segregated into only surface oxide. It was observed that Ge profile of SiGe layer was shown a less graded profile. And, in the second step with 60-nm-thick oxidation, Ge atoms in SiGe layer into Si layer-on-insulator was diffused further than a first step did and Ge atoms were segregated into surface oxide. It was observed that Si layer was shown a fully graded profile. Lastly, in the third step with 90-nm-thick oxidation, the diffusion of Ge atoms in SiGe layer into Si layer-on-insulator was finished completely and Ge atoms were segregated into both surface and buried oxides. It was confirm that Ge profile of SiGe layer was shown a Gaussian profile rather than a graded profile, and dislocation sink occurred. Therefore, our talk will focus on the explanation for the mechanism by which condensation method produces ε-SGOI via characterizing a surface property, SiGe thickness, a remained Si thickness on insulator, and Ge concentration in SiGe layer.

Ultrathin High-k Gate Dielectric Films on Strained-Si/SiGe Heterolayers

We have investigated the deposition of alternative gate dielectrics i.e., high dielectric constant (high-k) materials such as ZrO2 and TiO2 on strained-Si on relaxed SiGe and strained-SiGe layers. The strained-Si heterolayers generally acquire a high defect density during heteroepitaxy and also the high-k gate dielectric films are prone to point defects. These defects play an important role in determining the electrical properties of the deposited films and their reliability. Basic understanding of the physical and chemical nature of these defects may help to alleviate the reliability problems. In this paper, the nature of several point defects and trap centers created from both strained-Si substrates and high-k gate dielectrics itself has been studied in detail. Magnetic resonance technique has been used to study the chemical nature of the defects present at the interface and dielectric trapping defects present in strained-Si/high-k metal-insulator-semiconductor (MIS) capacitors. The physical nature and the quantification of the trapping/detrapping centers have also been studied under stressing (in both constant current and voltage modes). Time-dependent dielectric breakdown (TDDB) characteristics have been measured to study the reliability of the MIS capacitors.

Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs

Mobility and low-frequency (LF) noise were studied in tensile strained Si n- and pMOSFETs fabricated on relaxed SiGe virtual substrates. Both the impact of the channel orientation (〈1 1 0〉 or 〈1 0 0〉 on (1 0 0) Si) and the tensile strain were carefully investigated. Two types of virtual substrates were used; a thin relaxed SiGe layer (20% Ge) and a thick one (27% Ge). The strained Si nMOSFETs fabricated on the thin substrate showed similar LF noise level as in the reference devices, whereas the thick substrate caused severely increased LF noise in the nMOSFETs. The latter was linked to the higher Ge concentration and explained by possible misfit dislocations and increased defect densities, likely resulting from strain relaxation caused by ion implantation damage. On the other hand, considerably lower LF noise was achieved in the pMOSFETs on the thick SiGe. The channel orientation was not found to have a significant influence on the LF noise performance in any of the studied devices.

Characterization of strained silicon on relaxed SiGe layer made by H ion implantation and annealing in ultra-high vacuum ambient

Twenty-nanometer-thick Si cap layer/74-nm-thick Si 0.72Ge 0.28 epilayer/Si heterostructural sample was implanted by 25 keV H + ion to a dose of 1 × 10 16 cm −2 and subsequently annealed in ultra-high vacuum ambient at the temperature of 800 °C for 30 min. Rutherford backscattering/ion channeling (RBS/C), Raman spectra, high resolution X-ray diffraction (HRXRD) and atomic force microscopy (AFM) were used to characterize the structural characteristic of Si/SiGe/Si heterostructure. Investigations by RBS/C demonstrate that the Si 0.72Ge 0.28 layer show good crystal quality (21.1% of channel minimum yield). The relaxation degree of partially relaxed Si 0.72Ge 0.28 layer was around 74%, which was obtained by HRXRD. The computation process of the relaxation degree of strain in SiGe layer according to HRXRD rocking curve was also thoroughly introduced. Raman analysis revealed that stress, σ and strain, ε in the thin strained-Si layer were around 1.2 Gpa and 0.52%, respectively. In addition, the small surface roughness in the formed strained-Si/relaxed Si 0.72Ge 0.28 layer/Si heterostructural sample was observed via AFM image.

Highly-ordered SiGe-islands grown by dislocation patterning using ion-assisted MBE

Fabrication of device structures based on laterally self-ordered systems without the use of expensive and time-consuming nanolithography could have undoubted advantages. For such applications, it is proposed to use misfit dislocation networks from partially relaxed SiGe layers on (1 0 0) Si substrate as a template for the growth of highly ordered SiGe islands. Ion bombardment during molecular beam epitaxy of metastable SiGe layers leads to such a partial relaxation by misfit dislocation networks. The ions are generated by the interaction of the evaporated Si flux with the electrons in an electron beam evaporator, which causes a partial ionization of Si atoms in the molecular beam. We demonstrate by atomic force microscopy that subsequent growth of SiGe on such relaxed SiGe (25–50% Ge) layers leads to the formation of uniform three-dimensional islands highly ordered in 〈1 1 0〉 directions.

Safer alternative liquid germanium precursors for relaxed graded SiGe layers and strained silicon by MOVPE

Commercial strategy to graded SiGe buffer layers and “strained silicon” involves passing germane (GeH 4) gas or germanium tetrachloride (GeCl 4) vapors as the preferred germanium sources, along with a silicon source over a heated substrate. Today, one of the major limitations impacting the commercialization of SiGe technology is the lack of a commercially viable and safer process that eliminates hazards associated with GeH 4 and the excessively higher thermal budget associated with GeCl 4. The key to growing successful SiGe structures is thus a strategic deposition process that employs safer alternative germanium sources, and allows a wide growth temperature window without degrading the film properties and jeopardizing the environment, health and safety (EHS) aspects of overall operation. In this paper, we report on the development of safer alternative liquid germanium precursors along with the first successful use of a new organo germanium precursor, iso-butyl germane (IBGe) for the growth of high purity Ge and SiGe films. We also detail our strategy to identify the most appropriate candidates from a large number of organo germanium compounds along with initial results on SiGe films and high-quality epitaxial Ge films deposited using IBGe.

Deviations from ideal nucleation-limited relaxation in high-Ge content compositionally graded SiGe∕Si

The authors report the sudden rise in threading dislocation density in Ge-rich relaxed graded SiGe layers grown at higher growth temperatures (T>550°C). They attribute this rise in threading dislocation density in relaxed Ge to dislocation nucleation. This observation is contrary to conventional graded buffers in Si-rich material, where higher growth temperatures result in reduced threading dislocation densities (TDDs). Additionally, a coupling effect between the effective strain during graded buffer growth and the growth rate was observed, as evidenced by increased TDD values at reduced growth rates. They conclude that reduced growth rates allow more time for the surface to evolve (i.e., roughen) during growth, thereby trapping mobile dislocations and necessitating the nucleation of additional dislocations to continue relaxing the structure.

The Challenges of Ge-Condensation Technique

Ultra-thin SiGe films on insulator with high Ge fraction were fabricated through Ge condensation. To achieve that strained Si0.75Ge0.25 layers were grown epitaxially on SOI wafers and oxidized in O2 at 1150ºC for various times. Raman measurements and X-TEM revealed the importance of purity of oxidation ambient for the oxidation process. Traces of moisture in the oxygen flux accelerate the process causing a switch from dry to wet oxidation mechanism, leading to complete oxidation of the starting layer in only 1 hour. The crystal quality and overall uniformity of such layers however is poor. The use of 100% dry oxygen provides the necessary control over the oxidation process. This allowed relaxed SiGe layers with concentration of Ge up to 45% and higher to be obtained. X-TEM indicated good crystalline quality and uniform layers with no threading dislocations or other defects introduced during oxidation.

Comparison of SiGe Virtual Substrates for the Fabrication of Strained Silicon-on-Insulator (sSOI) Using Wafer Bonding and Layer Transfer

Different methods of preparing sSOI wafers have been analyzed. The initial virtual substrate wafers are characterized by a 17 - 20 nm thick strained silicon layer grown either on a thick relaxed SiGe layer on a graded buffer or on a thin SiGe buffer relaxed by He implantation. Bonding and layer transfer experiments using different oxide layers proved that strained silicon layers are completely transferred if designed PE-CVD oxide layers were used. For both types of virtual substrates the oxide layers are deposited on top of the strained silicon and bonded to non-oxidized (blank) silicon wafers. A perfect layers transfer is obtained for virtual substrates having thick SiGe buffer layers (type A) even at 350ºC, while annealing at 450ºC is required for substrates with thin SiGe buffer layers (type B). The lower annealing temperature for substrates of type A is caused by the lower activation energy for blistering. The hydrogen implantation is here into the SiGe. For type B substrates the hydrogen implantation is into the underlying Si requiring a higher temperature for layer splitting (higher activation energy for Si).

SSOI fabrication by wafer bonding and layer splitting of thin SiGe virtual substrates

Fabrication of strained silicon on insulator (sSOI) substrates by wafer bonding and layer splitting is described in this paper. The sSi layer of 20 nm thickness is obtained on an 8 in. virtual substrate that consists of a plastically relaxed SiGe layer grown epitaxially on Si(0 0 1) by chemical vapor deposition (CVD). The plastic relaxation of the initially pseudomorphic SiGe layer is mediated by helium implantation into the Si wafer below the SiGe/Si(0 0 1) interface and subsequent annealing. A SiO 2 layer is grown by plasma enhanced (PE) CVD on the sSi/virtual substrate prior to wafer bonding. The PECVD oxide layer is used to compensate the thermal stress existing at the bonding interface during annealing. The SiO 2/sSi/virtual substrate wafers are then implanted with hydrogen at a high dose (3.5 × 10 16 H 2 + cm −2) and subsequently bonded to Si(0 0 1) handle wafers. Subsequent annealing of the bonded wafer pair leads to the transfer of the implanted layer (containing the sSi layer) from the virtual substrate to the Si handle wafer. The final sSOI structure is realized by subsequent chemo-mechanical polishing followed by selective wet chemical etching. The sSOI substrate shows good thickness uniformity (∼20 nm) of the sSi layer over the entire 8 in. area and the strain measurements indicate a value of ∼0.66%.

Strained Si engineering for nanoscale MOSFETs

We have revealed a strain relaxation mechanism for strained Si grown on a relaxed SiGe-on-insulator structure fabricated by the bonding, dislocation sink, or condensation method. Strain relaxation for both the bonding and dislocation sink methods was achieved by grading the Ge concentration; in contrast, the relaxation for the condensation method was achieved through Ge atom condensation during oxidation. In addition, we estimated the surface roughness and threading-dislocation pit density for relaxed SiGe layer fabricated by the bonding, dislocation sink, or condensation method. The surface roughness and threading-dislocation pit density for the bonding, dislocation sink, and condensation methods were 2.45, 0.46, and 0.40 nm and 5.0 × 10 3, 9 × 10 3, and 0, respectively. In terms of quality and cost-effectiveness, the condensation method was superior to the bonding and dislocation sink methods for forming strained Si on a relaxed SiGe-on-insulator structure.

Investigation of dislocations in composition graded and strain relaxed SiGe epitaxial layer by cathodeluminescence

Dislocations in stair-like composition graded SiGe layer and relaxed SiGe layer with Ge composition of 15%, 20% and 20% have been investigated with chemical etching and cathodeluminescence (CL). Etch pit density in the s-Si region is contained with the order of 10 4 cm −2 and it is almost constant in the relaxed and graded SiGe layer with the order of 10 5 cm −2 for every Ge composition samples. From the observation of the cleaved surface, misfit dislocations pile up at the boundary in each layer and Ge composition changing regions. Defect relative luminescence lines (D1 and D2 lines) were observed, but D3 and D4 lines were not present in the present samples. It is found that the luminescence intensity ratio of D1 to D2 depends on acceleration voltage of CL. From these results, it is suggested that the amount ratio of dislocation type causing D1 and D2 changes with the depth from surface.

Modelling of strained-Si/SiGe NMOS transistors including DC self-heating

In this paper, a new model of surface-channel strained-Si/SiGe NMOSFETs is derived based on the extension of non-quasi-static (NQS) circuit model developed previously for bulk-Si devices. Basic equations of the NQS MOS model have been modified to account for new physical parameters of strained-Si and relaxed-SiGe layers. In addition, the device steady-state self-heating is efficiently included without employing the thermal-flow analog auxiliary sub-circuits. From the comparisons of modelling results with numerical simulations and measurements, it is shown that a modified NQS MOS including steady-state self-heating can accurately predict the DC characteristics of strained-Si/SiGe NMOSFETs.

Fabrication of strained-Si channel p-MOSFET’s on ultra-thin SiGe virtual substrates

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET’s (L-4.2 μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.

On the Mechanism of the Smart Cut Layer Transfer in Relaxed SiGe Layers

not Available.

Thermal Stability of a Reverse-Graded SiGe Buffer Layer for Growth of Relaxed SiGe Epitaxy

We have recently developed a novel reverse-graded (RG) buffer system, in which the Ge content decreases with distance from the Si interface. These thin (90 nm) RG layers are capable of supporting the growth of relaxed SiGe layers (85% relaxed) with defect densities as low as 10 5 /cm 2 . Good quality strained Si has also been successfully grown on these substrates. However, the thermal stability of this novel heterostructure has not been explored. In this paper, we establish, by high-resolution X-ray diffraction, Raman spectroscopy, atomic force microscopy, and transmission electron microscopy, that the heterostructure is stable up to 1000°C with no further strain relaxation in both the RG layer and strained Si layer. Hence, it is clear that this thin RG heterostructure is highly suitable as a buffer system for the growth of high-mobility strained Si or Ge devices.

Engineered substrates and their future role in microelectronics

Progress in lattice engineering, planar ultra-strained epitaxial layer growth, and layer transfer technology has resulted in the ability to create many engineered substrate types. In particular, a wealth of possibilities exists in the SiGe/Si system. Engineered substrates based on relaxed SiGe layers on Si with strained Si and Ge layers have resulted in long channel MOSFETs with ∼2× enhancement in NMOS drive current and more than 10× enhancement in PMOS drive current as compared to control Si MOSFETs. We have attempted to increase the NMOS drive current further by beginning to explore strained GaAs on relaxed SiGe layers on Si.

Influence of dislocations in strained Si∕relaxed SiGe layers on n+∕p-junctions in a metal-oxide-semiconductor field-effect transistor technology

We present an investigation of junction leakage in highly doped n+∕p-junctions, fabricated in strained silicon/relaxed SiGe substrates. The leakage is shown to scale linearly with the threading dislocation density of the virtual substrate, which allows to estimate minority carrier generation lifetimes in good agreement with literature values. Even the highest-defective substrates in this work give a junction leakage density below 100mA∕cm2, and are not expected to significantly increase the power consumption of metal-oxide-semiconductor field-effect transistor (MOSFET) technologies. Threading dislocations will increase the junction leakage by ∼1nA in a small number of transistors in MOSFET circuits, but are not expected to have a negative impact on yield.

Relaxed SiGe-on-insulator fabricated by dry oxidation of sandwiched Si/SiGe/Si structure

An improved technique is demonstrated to fabricate silicon–germanium on insulator (SGOI) starting with a sandwiched structure of Si/SiGe/Si. After oxidation of the sandwiched structure and successive annealing, a relaxed SiGe-on-insulator (SGOI) structure is produced. Our results indicate that the added Si cap layer is advantageous in suppressing Ge loss at the initial stage of SiGe oxidation and the subsequent annealing process homogenizes the Ge fraction. Raman measurements reveal that the strain in the SiGe layer is fully relaxed at high oxidation temperature (∼1150 °C) without generating any threading dislocations and crosshatch patterns, which generally exist in the relaxed SiGe layer on bulk Si substrate.