Channel Region Research Articles

Addition of en-APTAS to a Polythiophene Film for Enhanced NO2 Gas Sensing

With the aim of enhancing gas-sensor performance, we introduced N-[3-(trimethoxysilyl)propyl]ethylenediamine (en-APTAS) into poly(3-hexylthiophene) (P3HT) thin films. The P3HT films with en-APTAS as an additive showed superior gas-sensing performance compared with pristine P3HT films. The sensitivity of the gas sensor with en-APTAS was especially enhanced for NO2 gas because the en-APTAS has two amine groups that act as adsorption sites for NO2 gas molecules as a consequence of their strong binding energy. The P3HT film with 0.5 vol % en-APTAS fabricated on a OH-functionalized substrate exhibited the greatest responsivity (ΔID/I0 = 0.83) and highest response, recovery rates (ΔR/Δt = 0.26 and 0.004, respectively), and sensitivity (2.9%/ppm) among the investigated films. The superior performance of this film is attributed to the en-APTAS coupling-agent additive in the P3HT active layer concomitantly modifying the OH-functionalized substrate via a one-step spin-coating procedure. The increase in the abundance of adsorption sites in the channel region can induce more p-doping by NO2, leading to an increase of the hole carrier density and, thus, an increase of the current level in a p-type transistor gas sensor.

New insights into low frequency noise (LFN) sources analysis in GaN/Si MIS-HEMTs

We present a thorough investigation of the low frequency (LF) noise in the access and channel regions in GaN MIS-HEMT devices. The 1/f noise behaviour is caused by trapping/de-trapping processes which are well described by carrier number fluctuations (CNF) and correlated mobility fluctuation (CMF) models. To address the issue of LF noise in the access and channel regions of GaN MIS-HEMT devices, we have tested respectively “non-gated” and “gated” devices with different designs. The border trap density extracted in optimized devices at AlGaN/GaN and Al2O3/GaN interfaces is better than previously reported GaN data and close to silicon CMOS results. This enabled us to show a controlled LF noise level and even improved one, emphasizing the progress in the manufacturing process of advanced GaN technologies. Due to the gate channel shape of GaN MIS-HEMT devices with recessed gate, a new CNF/CMF noise model including access resistance noise source is also proposed. It enables a reliable parameter extraction in each channel region, authorizing device noise modeling over a large set of GaN MIS-HEMT process and design.

The ancient inhabitants of the Chonos Archipelago (~43°–47°S): Characterization of maritime hunter‐gatherers from Western Patagonia using mitochondrial DNA

AbstractBackgroundWithin the southern end of South America, Western Patagonia arises as an intricate region of channels, fjords, and islands. This region holds evidence of human occupation since ca. 14,500 cal years BP, with distinctive maritime adaptations developing around 7300 cal years BP. Historically, three major populations were characterized as part of these maritime traditions: Yámana, Kawésqar, and Chono. The arrival of European population had a profound impact in these communities, affecting their lifestyles, territory and population size and health. The northernmost populations, living within the Chonos Archipelago, were the most affected and the least known communities from Western Patagonia.ObjectivesThis research aims to characterize the mitochondrial DNA diversity of ancient individuals from the Chonos Archipelago, evaluating their genetic affinities with other ancient and present‐day populations from Patagonia.Materials and MethodsA total of 46 individuals from the region were sampled for ancient DNA analysis. Mitochondrial DNA haplogroups were characterized and compared with ancient and present‐day populations from Southern South America.ResultsAll individuals from the Chonos Archipelago belong to C and D haplogroups, particularly to C1b, C1b13, D1, D1g, and D4h3a5. As a group, the individuals from Chonos Archipelago lay closer to ancient individuals from Kawésqar territory, immediately south of them. Using mitogenomes, we characterized two new D4h3a5 lineages almost exclusively associated with populations from Western Patagonia.DiscussionOur results contribute to the understanding of the peopling and human interactions in Western Patagonia, suggesting these unique maritime traditions developed within local populations, genetically associated with earlier terrestrial populations.

The application of two-phase model to assess the nanofluid entropy generation in serpentine and double-serpentine heatsinks

The frictional and thermal entropy generation rates (S˙fr and S˙th) of two heatsinks with serpentine (Conf. A) and double serpentine (Conf. B) channels with water/silver Nano fluid (NF) were numerically investigated. The results demonstrated that the augmentation of nanoparticle concentration (φ) from 0% to 1% leads to decrease S˙th by 6.36% and 3.51% in Conf. A and Conf. B, respectively, for Re=500. The escalation of Re from 500 to 2000 increases this percentages to 9.93% and 7.51%, respectively. Also, the increase of Re from 500 to 2000 at a constant φ reduces S˙th by 63% and 68% in Conf. A and Conf. B, respectively, due to enhance the heat dissipation. Moreover, the increasing of φ from 0% to 1% decreases S˙fr by 12.41% in both configurations and at four studied Res due to decreasing the NF velocity. Besides, the escalation of Re from 500-2000 intensifies S˙fr nearly by 62% and 67% in Conf. A and Conf. B, respectively. The entropy contour plots reveal that S˙fr intensifies near the turn regions of the serpentine channels. Also, S˙th is intensifies at the entrance of heatsink channels due to the high temperature gradient at these points. Conversely, S˙fr escalates at the exit of the channels due to intensification of the vortexes formed at the turn parts and along the serpentine channel.

Anti-Clogging Performance Optimization for Shunt-Hedging Drip Irrigation Emitters Based on Water–Sand Motion Characteristics

To improve the irrigation quality and anti-clogging performance of the emitter, it is necessary to design and optimize its flow channel structure. The shunt-hedging drip irrigation emitter (SHDIE) flow channel is a new type of flow channel. Using computational fluid dynamics, by setting different conditions (such as particle size and injection position), the motion trajectory of sand particles and flow field distribution characteristics of the shunt-hedging flow channel were simulated. According to the simulation results, a new anti-clogging structural optimization scheme was proposed, and physical experiments verified its feasibility. The results showed that the flow index of the original flow channel (SHDIE1) and optimized flow channel (SHDIE2) were 0.479 and 0.486, respectively, which mainly relied on the shunting and hedging of water flow to energy dissipation. For sand particles with diameters of 0.05, 0.10, and 0.15 mm, the average values of the velocity amplitude ratio, η, were 0.9998, 0.9994, and 0.9991, respectively; the average values of the velocity phase difference, β, were −0.143°, −0.320°, and −0.409°, respectively. A larger sand particle diameter led to worse followability and a higher risk of blocking the channel. When the sand particles collided with the sensitive region of the flow channel, their movement direction would suddenly change, entering the vortex area. After colliding with the sensitive region of edge A, the maximum probability of sand particles entering the vortex area was increased to 87.5%, and then they stayed in the vortex area under the effect of the sensitive regions of edges B and C. After the sensitive regions were removed, the motion trajectories of sand particles became regular and smooth. The optimized flow channel’s (SHDIE2) anti-clogging performance was greatly improved by 60%, with a 1.46% loss of hydraulic performance. This study can provide theoretical support for designing the high anti-clogging emitter.

The Optimized Conformation Dynamics of the KcsA Filter as a Probe for Lateral Membrane Effects: A First Principle Based Femto-Sec Resolution MD Study.

We provide a high resolution, all-atom, femto-second molecular dynamics (MD) simulation of the passage of K+ ions and H2O molecules through the selectivity filter of the KcsA potassium ion channel, based on first principle physical methods. Our results show that a change in the length of the selectivity filter of as little as 3%, regardless of whether the filter is made longer or shorter, will reduce the K+ ion current by around 50%. In addition, further squeezing or stretching by about 9% can effectively stop the current. Our results demonstrate optimized conformational dynamics that associate an increased mobility of parts in the filter linings with a standard configuration, leading to maximized conduction rates that are highly sensitive to geometrical distortions. We discuss this latter aspect in relation to lateral membrane effects on the filter region of ion channels and the 'force from lipids' hypothesis.

Waveguide-Integrated MoTe2 p-i-n Homojunction Photodetector.

Two-dimensional (2D) materials, featuring distinctive electronic and optical properties and dangling-bond-free surfaces, are promising for developing high-performance on-chip photodetectors in photonic integrated circuits. However, most of the previously reported devices operating in the photoconductive mode suffer from a high dark current or a low responsivity. Here, we demonstrate a MoTe2 p-i-n homojunction fabricated directly on a silicon photonic crystal (PC) waveguide, which enables on-chip photodetection with ultralow dark current, high responsivity, and fast response speed. The adopted silicon PC waveguide is electrically split into two individual back gates to selectively dope the top regions of the MoTe2 channel in p- or n-types. High-quality reconfigurable MoTe2 (p-i-n, n-i-p, n-i-n, p-i-p) homojunctions are realized successfully, presenting rectification behaviors with ideality factors approaching 1.0 and ultralow dark currents less than 90 pA. Waveguide-assisted MoTe2 absorption promises a sensitive photodetection in the telecommunication O-band from 1260 to 1340 nm, though it is close to MoTe2's absorption band-edge. A competitive photoresponsivity of 0.4 A/W is realized with a light on/off current ratio exceeding 104 and a record-high normalized photocurrent-to-dark-current ratio of 106 mW-1. The ultrasmall capacitance of p-i-n homojunction and high carrier mobility of MoTe2 promise a high dynamic response bandwidth close to 34.0 GHz. The proposed device geometry has the advantages of employing a silicon PC waveguide as the back gates to build a 2D material p-i-n homojunction directly and simultaneously to enhance light-2D material interaction. It provides a potential pathway to develop 2D material-based photodetectors, laser diodes, and electro-optic modulators on silicon photonic chips.

Dynamic Interactions Between Brilliant Green and MscL Investigated by Solid-State NMR Spectroscopy and Molecular Dynamics Simulations.

The mechanosensitive ion channel of large conductance (MscL) is a promising template for the development of new antibiotics due to its high conservation and uniqueness to microbes. Brilliant green (BG), a triarylmethane dye, has been identified as a new antibiotic targeted MscL. However, the detailed binding sites to MscL and the dynamic pathway of BG through the MscL channel remain unknown. Here, the dynamic interactions between BG and MscL were investigated using solid-state NMR spectroscopy and molecule dynamics (MD) simulations. Residue site-specific binding sites of BG to the MscL channel were identified by solid-state NMR. In addition, MD simulations revealed that BG conducts through the MscL channel via residues along the inner surface of the pore sequentially, in which the strong hydrophobic interactions between BG and hydrophobic residues F23 and I27 in the hydrophobic gate region of the MscL channel are major restrictions. Particularly, it was demonstrated that BG activates the MscL channel by reducing the hydrophobicity of the F23 in the gate region by water molecules that are bound to BG. Taken together, these simulations and experimental data provide novel insights into the dynamic interactions between BG and MscL, based on which new hydrophobic antibiotics and adjuvants targeting MscL can be developed.

Design and research of normally-off β-Ga2O3/4H-SiC heterojunction field effect transistor

Ga2O3 is difficult to achieve p-type doping, which further hinders the development of Ga2O3-based power devices and is not conducive to the development of new devices with high power density and low power consumption. This paper expounds a β-Ga2O3/4H-SiC heterojunction lateral metal–oxide–semiconductor field-effect transistor (HJFET), which can make better use of the characteristics of PN junction by adding p-doped SiC in the channel region. Compared with the conventional devices, the threshold voltage of the heterojunction metal–oxide–semiconductor field-effect transistor (MOSFET) is greatly improved, and normally-off operation is realized, showing a positive threshold voltage of 0.82 V. Meanwhile, the off-state breakdown voltage of the device is up to 1817 V, and the maximum transconductance is 15.3 mS/mm. The optimal PFOM is obtained by simulating the thickness, length and doping of the SiC in each region of the epitaxial layer. This structure provides a feasible idea for high performance β-Ga2O3 MOSFET.

Human skeletal dysplasia causing L596P-mutant alters the conserved amino acid pattern at the lipid-water-Interface of TRPV4

TRPV4 is a polymodal and non-selective cation channel that is activated by multiple physical and chemical stimuli. >50 naturally occurring point-mutation of TRPV4 have been identified in human, most of which induce different diseases commonly termed as channelopathies. While, these mutations are either “gain-of-function” or “loss-of-function” in nature, the exact molecular and cellular mechanisms behind such diverse channelopathies are largely unknown. In this work, we analyze the evolutionary conservation of individual amino acids present in the lipid-water-interface (LWI) regions and the relationship of TRPV4 with membrane cholesterol. Our data suggests that the positive-negative charges and hydrophobic-hydrophilic amino acids form “specific patterns” in the LWI region which remain conserved throughout the vertebrate evolution and thus suggesting for the specific microenvironment where TRPV4 remain functional. Notably, Spondylometaphyseal Dysplasia, Kozlowski (SMDK) disease causing L596P mutation disrupts this pattern significantly at the LWI region. L596P mutant also sequesters Caveolin-1 differently, especially in partial cholesterol-depleted (~40 % reduction) conditions. L596P shows altered localization in membrane and enhanced Ca2+-influx properties in cell as well as in filopodia-like structures. We propose that conserved pattern of amino acids is an important parameter for proper localization and functions of TRPV4 in physiological conditions. These findings also offer a new paradigm to analyze the channelopathies caused by mutations in LWI regions of other channels as well.

Insecticide resistance in malaria and arbovirus vectors in Papua New Guinea, 2017–2022

BackgroundInsecticide resistance (IR) monitoring is essential for evidence-based control of mosquito-borne diseases. While widespread pyrethroid resistance in Anopheles and Aedes species has been described in many countries, data for Papua New Guinea (PNG) are limited. Available data indicate that the local Anopheles populations in PNG remain pyrethroid-susceptible, making regular IR monitoring even more important. In addition, Aedes aegypti pyrethroid resistance has been described in PNG. Here, Anopheles and Aedes IR monitoring data generated from across PNG between 2017 and 2022 are presented.MethodsMosquito larvae were collected in larval habitat surveys and through ovitraps. Mosquitoes were reared to adults and tested using standard WHO susceptibility bioassays. DNA from a subset of Aedes mosquitoes was sequenced to analyse the voltage-sensitive sodium channel (Vssc) region for any resistance-related mutations.ResultsApproximately 20,000 adult female mosquitoes from nine PNG provinces were tested. Anopheles punctulatus sensu lato mosquitoes were susceptible to pyrethroids but there were signs of reduced mortality in some areas. Some Anopheles populations were also resistant to DDT. Tests also showed that Aedes. aegypti in PNG are resistant to pyrethroids and DDT and that there was also likelihood of bendiocarb resistance. A range of Vssc resistance mutations were identified. Aedesalbopictus were DDT resistant and were likely developing pyrethroid resistance, given a low frequency of Vssc mutations was observed.ConclusionsAedes aegypti is highly pyrethroid resistant and also shows signs of resistance against carbamates in PNG. Anopheles punctulatus s.l. and Ae. albopictus populations exhibit low levels of resistance against pyrethroids and DDT in some areas. Pyrethroid-only bed nets are currently the only programmatic vector control tool used in PNG. It is important to continue to monitor IR in PNG and develop proactive insecticide resistance management strategies in primary disease vectors to retain pyrethroid susceptibility especially in the malaria vectors for as long as possible.Graphic abstract

Resolving the Unusual Gate Leakage Currents of Thin-Film Transistors with Single-Walled Carbon-Nanotube-Based Active Layers

Solution-processed single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) in the research stage often have large active areas. This results in unusual gate leakage currents with high magnitudes that vary with applied voltages. In this paper, we report an improved structure for solution-processed SWCNT-based TFTs. The unusual gate leakage current in the improved structure is resolved by patterning the SWCNT active layer to confine it to the channel region. For comparative purposes, this improved structure is compared to a traditional structure whose unpatterned SWCNT active layer expands well beyond the channel region. As TFT performance also varies with oxide layer thickness, 90 nm and 300 nm thick oxides were considered. The improved TFTs have gate leakage currents far lower than the traditional TFT with the same dimensions (aside from the unpatterned active area). Moreover, the unusual variation in gate leakage current with applied voltages is resolved. Patterning the SWCNT layer, increasing the oxide thickness, and reducing the top electrode length all help prevent a rapid dielectric breakdown. To take advantage of solution-based fabrication processes, the active layer and electrodes of our TFTs were fabricated with solution-based depositions. The performance of the TFT can be further improved in the future by increasing SWCNT solution incubation time and reducing channel size.

Potential model and simulation analysis of dual material gate vertical TFET with impact of interface trap charges

This paper presents modeling and simulation of the dual material gate vertical tunnel FET (VTFET-DMG) by including the interface trap charges. The interface trap charges are considered at the high-k and silicon substrate interface near the source and the channel region. The surface potential model is developed here by utilizing the 1-D and 2-D Poisson equations solved with different boundary conditions after dividing the whole device into eight different regions. The parabolic approximation is assumed to find the numerical solution of the Poisson equations. The same device is also designed and simulated in the Silvaco TCAD simulator with the inclusion of the impact of the interface trap charges and the outcomes of the simulations are compared with the modeled results. The variation of the surface potential with the increase in positive interface charges and negative interface charges is plotted and analyzed. It is seen that the surface potential enhances with the increase in positive interface charges and it reduces with the increase in the negative interface trap charges. We use the dual material gate approach in proposed structure to show an overall increase in the performance of the device. Incorporating the high-K gate oxide in the presence of interface traps improves the device's reliability for low power utilization.

Investigation of Flow-Induced Noise Characteristics in the Oblique Flow Pump

An oblique flow pump is widely used in farmland irrigation and drainage, water transfer projects, thermal power generation, and other fields. However, unstable flow factors in the oblique flow pump easily lead to pump vibration and noise. To improve the stability of pump operation and optimize the operating environment, it is necessary to study the flow-induced noise characteristics of oblique flow pumps. In this paper, CFD and noise simulation software are used to calculate the flow field and sound field of the oblique flow pump. The internal flow characteristics and flow-induced noise characteristics of the oblique flow pump were studied. The results show that when the flow rate of the oblique flow pump deviates from the optimal operating point, especially in the small flow rate, due to the phenomena of backflow and flow separation, more high-energy vortices are produced in the flow channel, and the vortices are distributed in a wide area, which will cause greater flow-induced noise. It is found that with the increase in flow rate, the sound pressure level of flow noise in the inlet channel gradually decreases, the sound pressure level in the guide vane region first decreases and then increases, and the sound pressure level is the lowest at 1.0Q. Generally speaking, the noise sound pressure level in the outlet channel region of the pump also gradually decreases. In addition, at the blade frequency, the radiated noise of the oblique flow pump can show dipole characteristics under various flow conditions, and the radiation level of sound pressure increases with the increase in flow rate. This paper can provide a theoretical basis for the mechanism research and control strategy of flow-induced noise in oblique flow pumps.

A Uni-gate vertical power MOSFET with improved figure of Merits: Design and analysis

In this paper, we propose and analyze a single buried gate power MOSFET structure. The structure uses single gate buried under the source and channel region with its dimensions optimized to get the best Ron-BV tradeoff. The device exhibits a good scaling property without performance degradation, which our previous structure of dual buried gates power MOSFET lacks because of the coupling effect of the two gates. The performance of the dual gates device depends largely on the length of the gates as well as on the separation between them. A performance degradation is observed while scaling it, in order to reduce its specific ON resistance. The proposed single gate device eliminates the coupling effect of the two gates allowing a better scaling of the device together with decreased process sensitivity. The scaling reduces the active area of the proposed device, resulting in the lowering of its specific ON resistance, without any significant change in its breakdown voltage. The reduced gate coupling also allows a high drift doping which further reduces the on resistance. The simulation results using TCAD device simulator shows that the proposed device possess a specific ON resistance of 25.31mohm.mm2 at a breakdown voltage of 68 V, resulting in a Baliga’s Figure-of-merit (FOM1) of 17.99 MW/cm2, which is highest among the other reported non RESURF devices in the literature. This is achieved in parallel with the reduced gate charge resulting in a good reduction in its other figure of merit, FOM2 (RspxQsp).

Flow Dynamics and Analyte Transfer in a Microfluidic Device for Spatial Two-Dimensional Separations

In the last decade, chip-based separations have become a major area of interest in the field of separation science, especially for the development of “spatial” two-dimensional liquid chromatography (xLC × xLC). In xLC × xLC, the analytes are first separated by migration to different positions in a first-dimension (1D) channel and subsequently transferred with the aid of a flow distributor in a perpendicular direction to undergo a second-dimension (2D) separation. In this study, several designs for 2D separations are explored with the aid of computational fluid dynamics simulations. There were several aims of this work, viz. (1) to investigate the possible anomalies arising from the location of analyte bands in the first-dimension channel before transfer to the second dimension induced by the flow distributor, (2) to study the distribution ratio of the analytes across the different outlets of the 1D channel, and (3) to study the flow behaviour confinement in the flow distributor. In all designs, the simulated absolute flow velocity was not equal in all regions of the 1D channel. The extreme segments showed higher velocities compared to the central zones. This will eventually influence the migration times (first moments) and the variances (second moments), as confirmed by CFD results. The study has contributed to the understanding of the effects of the peak locations and, ultimately, to progress in spatial 2D-LC separations.

Compressive Strained Si1-XGex Channel for High Performance Gate-All-Around Nanosheet Transistors

As scaling of conventional FinFET architecture to achieve target transistor density and performance becomes more complex and difficult, it is essential to attain a next generation transistor architecture. Horizontal Gate-All-Around (hGAA) nanosheet (NS) devices have attracted attention as a candidate to replace FinFETs at the 5nm technology node and beyond due to their excellent electrostatics and short channel control. Compared to scaled FinFET, stacked GAA NS offers circuit performance improvements with increased effective width per active footprint while also enabling gate length scaling. Exploring performance improvement techniques, such as channel strain engineering, is important for next generation CMOS technologies. It is difficult, however, to effectively induce strain into the channel region using source/drain stressors in scaled GAA NS structures due to reduction of the stressor (embedded SiGe in source/drain region) volume as transistor dimension shrinks. In addition, strain relaxation of source/drain stressors caused by introduction of crystalline defects decreases effectiveness to induce strain into the channel region. This is more pronounced by the fact that achieving superior epitaxial growth is more difficult on the GAA NS device structure due to the presence of inner spacer dielectric. Therefore, we proposed a stacked GAA NS pFET device with compressively strained SiGe channel. The SiGe channel NS devices were fabricated using Si NS channel trimming by selective isotropic dry etch and selective SiGe epitaxial growth techniques after the Si NS channel release (Fig. 1). This is the preferable scheme in terms of strain retention in the SiGe channel NS region since there are no patterning processes that cause strain relaxation during downstream processing.To investigate the device characteristics of SiGe NS devices, we fabricated strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET and investigated the crystallinity and strain in the channel region. Fig. 2 contains cross-sectional TEM images across the gate after Si0.7Ge0.3 channel formation. We observed no visible crystalline defects in the 4 nm-thick Si0.7Ge0.3 layer grown on the 2 nm-thick trimmed Si NS, indicating superior crystallinity of Si0.7Ge0.3 layer. To investigate strain in the nanoscale strained SiGe NS channel structures, Precession Electron Diffraction (PED) characterization was performed to evaluate lattice deformation of the stacked SiGe NS channel with 4 nm-thick Si0.7Ge0.3 epitaxial growth. Lattice deformation values are defined as the difference between in-plane lattice constants and the Si lattice constant, normalized by the Si lattice constant. Fig. 3 shows in-plane lattice deformation contour maps in the region of the stacked SiGe NS channel obtained from both X-cut (across the gate) and Y-cut (along the gate) for the SiGe NS structure with sheet width of 20 nm. The in-plane lattice deformation values were extracted from the middle of the SiGe NS channel as shown in Fig. 4. Preservation of half the amount of strain along the channel direction ([110]) was confirmed whereas strain along the NS width direction ([1-10]) was found to be almost fully relaxed due to elastic relaxation. This results in the Si0.7Ge0.3 channel being uniaxially stressed. The compressive stress along the channel direction estimated from the [110] lattice deformation is ~1 GPa.Normalized hole mobility in the representative Si1-xGex channel NS pFET as a function of inversion carrier density (Ninv) is shown in Fig. 5. The hole mobility of Si1-xGex channel (x = 0.35) with Si cap is almost 100% higher than that of Si NS channel. The mobility benefit of Si1-xGex channel is attributed to reduced effective hole mass along the transport direction caused by a high compressive strain in the Si1-xGex channel.The technique demonstrated in this study for forming compressively strained SiGe channel NS has great potential to improve pFET device performance for next generation of CMOS logic in GAA Nanosheet technology. Figure 1

(Digital Presentation) Instability of α-Si:H TFTs under Simultaneous Ultraviolet Light Illumination and Different Bias Stresses

Hydrogenated amorphous silicon thin-film transistors (α-Si:H TFTs ) are widely applied in liquid crystal displays (LCD). They can be used as not only the switching devices in the panel but also the scan driving circuit in the active-matrix liquid crystal displays (AMLCD), as well as large-area optical imaging sensor arrays. The α-Si:H could be deposited on the glass or plastic substrates at the low temperature, good uniformity in the large area, and the process is relatively mature, so it is still a competitive material. This study would investigate the deterioration of the α-Si:H TFTs under various bias stressing conditions with and without UV light.For the DC bias stress on the gate terminal, the electron trapping within the gate dielectric under positive bias would cause the threshold voltage (Vth) to shift to the positive direction, but the hole trapping under negative bias would cause the Vth to shift to the negative one. Furthermore, under the DC bias stress, the UV light illuminates the TFTs simultaneously, and the active layer of TFTs would generate additional electrons and holes, which would increase the trapping probability of charges and the amount of degradation and recovery. Both effects of the electron capture in the dielectric and defects creation in the channel would cause the Vth to shift to the positive direction, so the degradation of TFTs under positive bias stress is relatively serious. The increment of the subthreshold swing of TFTs under negative bias stress would be much larger than those under positive one, and the captured holes are easily released in the reverse sweeping mode, leading to the decrease of the drain current. Therefore, the amount of degradation and recovery of the TFTs under negative bias stress is relatively small in the reverse sweeping mode, because the energy barrier of holes is smaller than that of electrons in the interface of α-Si:H/SiNx.For the experiments of AC bias stress on the gate terminal with UV light illuminating simultaneously, the frequency of AC signal is fixed at 10 KHz. It could be found that the leakage current in the cut-off region under negative bias (-35 ~ 0 V) stress would increase with the stress time lasting, which shows that the holes are trapped within the gate dielectric closer to the active layer at the high frequency. These shallow positive trapped charges would attract the electrons to accumulate in the channel region, which causes the drain current to increase gradually. However, under bipolar bias (-17.5 ~ +17.5 V) stress, the charge trapping would first dominate the Vth degradation of TFTs, and then the defect states creation would gradually dominate the change of the Vth as the stress time increasing, which causes the Vth first to shift to the negative direction and then to positive one.For another experiments of AC bias stress on the gate terminal without UV light illumination, the frequencies of AC signals are fixed at 10 Hz and 10 KHz with different ranges of biasing voltages. It could be found that the Vth degradation of TFTs at different frequencies under the higher positive bias cycle (0 ~ +35 and -10 ~ +25 V) is not obviously different, mainly because the speed of electron’s accumulation and disappearance in the channel region could keep up with the switching speed of AC signals. However, it could be found that during the higher negative bias cycle(-35 ~ 0 and -25 ~ +10 V), the amount of change in the Vth at low frequency is relatively larger than that at high frequency, which is due to the RC delay effect of the n+α-Si:H layer on the holes under negative bias stress. To investigate the recovery behavior of TFTs, including the direction and amount of the Vth change in the resting time, we could know the dominating mechanism that leads to the TFT’s degradation. And the probably balanced AC bias stress condition is about -10 ~ +25 V. As the magnitude of negative biasing voltage increases, the holes capture within the gate dielectric would increase, and the drain current in the cut-off region also increases.Finally, the β parameter, in the formula of ΔVth= Atβ, is obtained by fitting the trends of ΔVth v.s. stress times. The value of β parameter would exhibits the influence of different mechanisms on the degradation of TFTs stressed by different bias conditions and with/without UV light illumination over the stressing time. And these results are consistent with above experimental data.

(Digital Presentation) Influence of Fin Width Modulation on Nanoscale FinFET

ABSTRACT In the present research work, the influence of Fin width thickness variation on the electrical performance parameters have been performed for the FinFET device. Various Fin angle (i.e., θ) have been considered to analyze the effect of Fin thickness variations. All the analyzed results have been compared with the ideal FinFET (i.e., θ = 0) device to observe the effect of angle variation on threshold voltage (VTH), Transconductance (gm), Gate current (IG) and Drain Induced Barrier Lowering (DIBL). In addition, the impact of Fin width thickness variations has been used to realize the inverter Voltage Transfer Characteristics (VTC). The characteristics comparison reveals that including the effect of Fin width improves the device performance of FinFET devices. INTRODUCTION The FinFET device has been considered as a future candidate for VLSI circuit design and manufacturing. Compared with planar technology, the FinFET device shows reduced Short Channel Effects (SCEs) and improved electrostatic control. However, device variability poses a severe threat to downscaling FinFET dimensions in the nanoscale regime because non-uniformity has a significant influence on short-channel devices [1, 2]. In the fabrication of FinFET devices, the effect of the nonrectangular Fin shape must be carefully considered because the Fin thickness of the fabricated FinFET differs from the ideal shape. It is found that it is difficult to achieve a perfect rectangular Fin shape due to Line Edge Roughness (LER) and Line Width Roughness (LWR) [3]. In previous research works, authors considered the variations introduced in the vertical direction of the Fin while ignoring the fact that Fin width fluctuates in the lateral direction too [4]. This lateral Fin fluctuation introduces significant errors during performance parameter analysis. Therefore, this present research work focused on fluctuations in the Fin in the lateral direction. Here, the effects of non-uniformity on electrical performance parameters such as VTH, gm, IG and DIBL have been analyzed and compared with the ideal FinFET device. Furthermore, the impact of these variations is incorporated into the realization of inverter VTC characteristic. DEVICE DESIGN AND RESULT ANALYSIS Fig. 1(a) shows the full 3D view of the FinFET device. The doping concentration of the Source/Drain (S/D) region is maintained at 1×1020 cm-3 . Here, channel thickness (Tsi ) and gate oxide thickness (tox ) are 8 nm and 1 nm, respectively. Titanium Nitride (TiN) metal has been employed as the gate electrode because TiN shows low resistivity, high melting, thermal stability, and compatibility with the standard CMOS process [5]. To analyze the effects of fin width variation on the performance parameters of FinFET, the non-uniformity has been shown in Fig. 1(b). Here, Tsi fluctuations are approximated as a linear slope, making an angle (θ) to X-axis in the range of -70 to 70 to exaggerate the width variation effects. A Positive angle means the drain area is more significant compared to the source area and vice versa. Fig. 2 displays the VTH and DIBL variations against the Fin width variation. It has been realized that for Fin thickness variation from -70 to +70 there is a shift in threshold voltage (VTH ) of 6.12% and 4.08%, respectively. However, it is also observed that the non-uniform Fin width improves the DIBL for the FinFET device. This is due to the modulation of the effective S/D area with the channel region. CONCLUSIONS AND FUTURE ASPECTS The effect of Fin width thickness variation is increasing as the feature size of the FinFET device reduces. This work realized that the linear variation in the overall Fin width thickness introduces comparable variations in electrical performance parameters for FinFET device. For instance, there is a significant improvement in DIBL for Fin thickness variation from -70 to +70 because these variations are directly correlated to the Fin thickness reduction. These insights will allow technologists and designers to capture a valid performance characteristic for Fin width variations effects to meet future design challenges in the nanometer regime. REFERENCES [1] A Khakifirooz, IEEE Trans. Elect. Dev., vol. 55(6), pp. 1401-1408, 2008.[2] RS Rathore, IEEE 4th International Conference on Signal Processing, Computing and Control (ISPCC), Solan, 2017, pp. 377-380.[3] RS Rathore, Superlattices and Microstructures, vol. 113, pp. 213-227, 2018.[4] X Wu, IEEE Trans. Elect. Dev., vol. 52(1), pp. 63-68,2005.[5] AR Brown, IEEE Trans. Elect. Dev., vol. 54(11), pp. 3056-3063, 2007. Figure 1

(Digital Presentation) Stacked Nanosheet FETs and Beyond

Si FinFETs have been used in the industry for mass production of advanced technology nodes [1-3]. Recently, the horizontal gate-all-around (GAA) transistors are considered as promising candidates to replace FinFETs due to the excellent electrostatics and short channel control [4-6]. The GAA architecture with vertically channel stacking can further enhance the drive current for a given footprint to achieve high performance and area scaling [7]. Moreover, high mobility channel is an attractive option to boost the drive current thanks to its intrinsic higher mobility as compared with Si [8]. Furthermore, a novel TreeFET architecture [9] as a combination of stacked nanosheets and additional fin interbridges (IBs) between nanosheets can enhance ION per footprint.In this work, we demonstrate the 8 stacked Ge0.75Si0.25 nanosheets with high inter-channel uniformity and the 7 stacked Ge0.95Si0.05 nanowires with record ION per channel footprint for nFETs [10, 11]. The highly stacked 8 Ge0.9Sn0.1 nanosheet pFET with ultrathin bodies and thick bodies are demonstrated for low power and high performance [12, 13], respectively. Furthermore, TreeFETs can increase Weff per footprint for high performance devices beyond FinFETs and nanosheets.The epilayers with 8 undoped and fully strained Ge0.75Si0.25 layers sandwiched by 9 P-doped Ge sacrificial layers (SL) were grown on the Ge buffer by CVD epitaxy. The S/D and channels of the 8 stacked Ge0.75Si0.25 nanosheets are fabricated by the same epilayer structures without S/D regrowth. The doping of S/D is obtained by the heavily P-doped Ge SLs by annealing, while the channel is undoped to reduce the impurity scattering. H2O2 wet etching was used to etch the Ge SLs in channel region. The etching selectivity of Ge over Ge0.75Si0.25 is attributed to the Si content in GeSi layers and the enhanced etching rate of Ge SLs by heavily doped phosphorus [14]. To further improve the drive current, [Si] in GeSi channels is decreased to 5% to ensure the electrons populated in L4 valleys with small mt. In addition to channel stacking, TreeFET combining with FinFETs and stacked nanosheets is demonstrated to enhance Weff per footprint. IBs of TreeFETs were formed by well-controlled H2O2 wet etching. With adequate etching selectivity and optimized etching time, the SLs were partially removed to form the IBs between the nanosheets for extra conduction channels.Strained GeSn has higher hole mobility than Ge to increase ION for pFET [15] due to the hole effective mass reduction under compressive strain. Recently, the radical-based highly selective isotropic dry etching (HiSIDE) was reported to form the stacked GeSn nanosheets [16-18]. However, the challenge of Ge-based channel is the large IOFF due to the small bandgap [15-20]. Ultrathin body device can effectively reduce the IOFF [21], but the mobility degradation is observed as the channel thickness decrease below 5nm due to surface roughness scattering [22]. However, the high mobility GeSn can afford some mobility loss due to the ultrathin body. By combining the high mobility channel and the large number of stacked nanosheets, the ION can be further improved with the suppression of IOFF by the ultrathin body. The 11nm Ge0.9Sn0.1 channel layers sandwiched by 8nm Ge0.97Sn0.03 caps, 3nm Ge caps, and 24nm Ge:B SLs were grown repeatedly on the Ge buffer. The thin double Ge0.97Sn0.03 caps can provide sufficient etching selectivity and prevent the channel bending. The heavily B-doped Ge SLs are used to reduce the S/D resistance. The significant IOFF reduction of the GeSn ultrathin bodies is attributed to the quantum confinement effects. The quantum confinement energy of 170meV in 3nm Ge0.9Sn0.1 ultrathin body is simulated by TCAD. The enlarged bandgap results in the suppression of IOFF and yields the record high ION/IOFF~107 of 8 stacked GeSn ultrathin bodies among GeSn/Ge 3D pFETs.Simple wet etching can reach the sufficient selectivity to fabricate the highly uniform Ge0.75Si0.25 nanosheets and the Ge0.95Si0.05 nanowires. The 3nm Ge0.9Sn0.1 ultrathin bodies with high inter-channel uniformity are demonstrated to reduce the IOFF. Highly stacked Ge0.9Sn0.1 thick nanosheets can improve the ION. TreeFET with the process flow similar to stacked nanosheets are the promising candidates for technology node scaling. Even higher number of stacked channels (>8) and extremely scaled ultrathin bodies (<3nm) are expected to further enhance the ION and to increase the ION/IOFF for advanced CMOS scaling. Acknowledgements- This work is supported by MOST (110-2218-E-002-030-, 110-2622-8-002-014-, 110-2218-E-002-034-MBK, and 110-2218-E-002-042-MBK) and MOE (NTU-CC-111L892001), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated. Figure 1