Regenerative Comparator Research Articles

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.

High Speed Comparators for Analog-To-Digital Converter

High speed devices such as ADC, operational amplifier are of great importance and for this high speed application, a major thrust is given towards low power methodologies. Minimization in power consumption in these device can be achieved by smaller feature size processes. Dynamic comparator are being used in today's A/D converters extensively because of their speed , lesser power dissipation , zero static power consumption and full-swing digital level output voltage in shorter time duration. Back to back inverter in these dynamic comparator provides positive feedback mechanism which convert a smaller voltage difference in full scale digital level output. A pre-amplifier based comparator can amplify a small input voltage difference to a large enough voltage to overcome the latch offset voltage and reduce the kickback noise. However the pre- amplifier based comparator suffer large static power consumption as well as reduced intrinsic gain with the reduction of the drain to source resistance due to continuous technology scaling. Keyword: Comparators ,High speed Analog-to-digital converter ,Regenerative comparator.

Mitigation of sampling distortion in regenerative comparators by passive source degeneration

Presented is a scheme for regenerative comparators to suppress the induced input-dependent sampling distortion and also to alleviate the impact of substrate noise coupled to the comparator. The proposed scheme is based on the concept of source degeneration and is realised by incorporating a resistor at the source terminal of the sampling transistors. The scheme is evaluated with transient simulations, by characterising the output waveform jitter of the comparator with eye diagrams, and it is proven effective in the presence of high input signals and substrate noise.

Application of Subharmonic Injection Locking of LC Oscillators to LO-Based Phase-Shifting Phased-Array Architectures

A ninth-subharmonic injection-locking scheme is proposed for local oscillator (LO) phase-shifting-based phased-array architectures operating in the ISM band at 24 GHz. The presented architecture employs a phase-shifter at the ninth subharmonic, a high-speed regenerative comparator, and a negative-gm oscillator to synthesize multiple phases of ninth-harmonic LO signals from a 2.41-GHz reference at the destination and in close proximity to the RF/millimeter-wave front-end mixers with first LO at 21.69 GHz. A digital phase-shift calibration technique is discussed. The reported LO phase-shifting and synthesis scheme is implemented in IBM's 130-nm CMOS technology and consumes a total of 32 mA per LO element from a 1.2-V supply. The injection-locked oscillators have a phase-noise performance of - 107.17 dBc/Hz at 1-MHz offset from 21.51 GHz. The maximum phase-shift error at 21.69 GHz is 9.86° and 2.1° before and after calibration, respectively.

Analyzing and modeling the performance degradation of flash A/D converters due to substrate noise coupling

This paper presents a model to evaluate the impact of substrate noise on a CMOS regenerative comparator and moreover to predict the resulting performance degradation of a flash analog-to-digital (A/D) converter. The proposed approach initially relates substrate noise to the induced timing uncertainty of the comparator by means of an analytical linear model. In particular, the analysis first focuses on analyzing and expressing the resulting non-uniform sampling distortion in regenerative comparators in the presence of a deterministic ground bounce. Two sources of distortion are identified and evaluated: the input-dependent and the substrate noise-dependent one. For each error contributor, the analysis investigates two cases of timing error, based on the frequency correlation of the interfering signal with the sampling clock. The properties (number and power of distortion tones) of the sampling error spectrum are found to be highly dependent on the spectral content of the interfering signal and the sampling clock, while the model captures accurately the induced distortion. Subsequently, the linear model is extended to estimate the degradation of flash A/D converters and is utilized to predict the performance of practical flash and time-interleaved converters in the presence of substrate noise.

Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compensated for by calibration, noise can irreparably hinder performance and is less straightforward to be accounted for at design time. This paper presents a method to estimate the input referred noise in fully dynamic regenerative comparators leveraging a reference architecture. A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations. The resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors. Analysis results are validated by comparison with electrical simulations and measurement results from two ADC prototypes based on the reference comparator architecture, implemented in 0.18-mum and 90-nm CMOS technologies.

A regenerative comparator structure with integrated inductors

We employ on-chip inductors to improve the sampling speed and power consumption of regenerative comparators. Since these inductors are far smaller than those used in typical RF designs, the addition of inductors has little impact on area. Simulations based on accurate inductor models indicate more than a doubling of comparator sampling speed for a given power consumption, or a halving in power consumption for a given sampling speed. We present a detailed analysis of the new scheme. The technique is verified with test measurements of 16 comparators, implemented in 0.18-/spl mu/m digital CMOS, sampling at 3.84 GHz.

Reduced-kickback regenerative current comparator for high-speed switched-current pipeline analogue-to-digital converters

A reduced-kickback regenerative current comparator based on a master-slave structure is presented. The master and slave comparators first operate concurrently but, soon, the master's operation is inhibited to prevent the extreme voltage surges, or kickback, from disturbing the driving memory while the slave circuit is allowed to regenerate and produce a valid digital output. Simulations indicate that practically no accuracy degradation in the driving memory cell is detected whereas the same operation using the elementary comparator disturbs the accuracy by more than 4 bits. Designed in a standard 0.35 µm 3.3 V digital CMOS technology, the master-slave comparator achieves a sampling speed of 100 MS/s with 7.5 bit resolution, while dissipating 290 µW of power from a single 1.8 V supply.

Mixed-mode Schmitt trigger equivalent circuit

A circuit implementing the regenerative comparator or Schmitt trigger function is presented. While the traditional Schmitt trigger implements the hysteresis levels by means of positive feedback in an analogue loop, our circuit implements hysteresis by digitally processing the output of two comparators operating in open-loop mode. The threshold levels of the new circuit can be independently set and fine-tuned which is not the case in many traditional Schmitt trigger implementations.

A digital dual-slope analogue to digital convertor

The bucket-brigade charge transfer principle can be used to design a switched capacitor integrator without using operational amplifiers. This integrator can replace the conventional RC-active integrator of the dual-slope convertor. When combined with a regenerative comparator circuit, a compact A/D convertor can be fabricated using conventional NMOS technology.

A Schmitt Trigger Design Technique for ‘Logic-Noise-Spike’ Elimination

A simple graphical procedure is introduced to optimise the design of a regenerative comparator (Schmitt trigger) capable of eliminating from a logic voltage waveform both positive-going ‘noise spikes’ contaminating the ‘0’ level (positive logic convention) and negative-going noise spikes contaminating the ‘1’ level.

Stabilizing the threshold difference of balanced diode regenerative comparators

Stabilizing the threshold difference of balanced diode regenerative comparators

Calculation of the threshold of a regenerative diode comparator

Calculation of the threshold of a regenerative diode comparator

A Transistorized Fail-Safe High-Low Trip

The paper describes a novel transistorized trip circuit which was designed according to A.C. fail safe principles, the circuit trips being on high and low levels, thus indicating off normal input conditions. Both levels are detected by a single regenerative comparator. The output decays within 3 msec after a trip condition, independent of input signal slope or level. The circuit posseses an inherent static trip state lock.