Reference Clock Research Articles

Design and Implementation of Image Acquisition and Signal Transmission Functions based on FPGA

Abstract In recent years, video network monitoring systems have evolved rapidly, from the first generation of digital-analogue systems to the fully IP-based systems. Based on the FPGA core, this design focuses on image acquisition and information transmission. The FPGA expansion board contains several peripheral modules, including the OV7670 camera captures images, DRAM stores data, and FIFO handles cross-clock domain signal transmission. While the reference clock is 40ns, in this system, the clock period is 20ns, making two clock cycles equal to one reference clock cycle. Then, two counters are used, one is the reference clock and another is the line synchronization (cnt1) to count 800 clock cycles per line. The end of a line is indicated by end_cnt0, and FIFO data is stored in SDRAM. Configuring the VGA display driver allows image data to be transmitted and displayed on the VGA screen. The system features a simple structure, high resource utilization, and strong reliability.

A Mixed Approach for Clock Synchronization in Distributed Data Acquisition Systems.

Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment.

Network Time Protocol based Black Box Timing Accuracy Analysis for Internet of Things Devices

With large-scale Cyber-Physical Systems (Internet of Things) deployments, the low-cost networked devices are becoming ubiquitous. Time stamping of events is a basic requirement and it is crucial for distributed/isolated systems/devices to work in unison. The system clocks of these devices are not very stable and their behaviour is affected by ageing and environmental conditions. A clock’s timing behaviour is generally analysed independently by comparison to a highly stable standard reference clock using specialized instruments. Network Time Protocol (NTP) is widely used for time synchronization over computer networks. As the NTP server clock is more stable in comparison to a client’s system clock, the variation in the end device’s clock offset values with respect to the NTP server clock over a long time can be considered for analysing the behaviour of the end device’s clock. This paper presents a method for analysing clock behaviour based on NTP messages. A computer programme is developed, which utilizes an open-source NTP client library to exchange NTP messages and records end device’s system clock’s offset variations over time for a given periodicity to analyse the behaviour. This black box analysis approach does not require any direct access to the end device’s clock circuit. The solution may be useful for analysing clock behaviour for long-term stability under actual environmental conditions, for deciding time synchronization periodicity to optimize the number of synchronization packet exchanges, and for pre-deployment timing stability assessment of devices for deployment scenarios having intermittent/non-availability of periodic time synchronization.

A 0.037 pJ K2$\text{K}^2$ 338 pW temperature sensor based on dynamic leakage‐suppression logic

AbstractThis letter introduces an ultra‐low‐power temperature sensor utilizing dynamic leakage‐suppression (DLS) logic and thoroughly analyses its working principle. The sensor effectively tackles the weak pull‐up challenge inherent in DLS logic ensuring its compatibility with standard digital logic. By capitalizing on the super cut‐off attribute of DLS logic, the frontend of the sensor achieves ultra‐low power consumption, without compromising on measurement precision or the breadth of the temperature range. The digital part of the proposed utilizes the output frequency of the sensor's frontend as the clock source, in conjunction with an external 50 Hz reference clock, achieving a low overall power consumption. The frontend of the temperature sensor was fabricated using a 180 nm process, occupying a minimal area of 374 . The digital part of the circuit is implemented using FPGA. Following a two‐point calibration and system error removal, the sensor, operating at a supply voltage of 0.8 V, demonstrated a error of across the temperature range of −20 to 125 . At 25 , the resolution figure of merit of the sensor was 0.037 pJ , with a maximum voltage sensitivity of 4.2 .

Design and Simulation of Clock Divider using VHDL

This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

Comprehensive Analysis on GPS Carrier Phase under Various Cutoff Elevation Angles and Its Impact on Station Coordinates’ Repeatability

When processing the carrier phase, the global navigation satellite system (GNSS) grants the highest precision for geodetic measurements. The analysis centers (ACs) from the International GNSS Service (IGS) provide different data such as precise clock data, precise orbits, reference frame, ionosphere and troposphere data, as well as other geodetic products. Each individual AC has its own strategy for delivering the abovementioned products, with one of the key elements being the cutoff elevation angle. Typically, this angle is arbitrarily chosen using generic values without studying the impact of this choice on the obtained results, in particular when very precise positions are considered. This article addresses this issue. To this end, the article has two key sections, and the first is to evaluate the impact of using the two different cutoff elevation angles that are most widely used: (a) 3 degrees cutoff and (b) 10 degrees cutoff elevation angle. This analysis is completed in two major parts: (i) the analysis of the root mean square (RMS) for the carrier phase and (ii) the analysis of the station position in terms of repeatability. The second key section of the paper is a comprehensive carrier phase analysis conducted by adopting a new approach using a mean of the 25-point average RMS (A-RMS) and the single-point RMS and using an ionosphere-free linear combination. By using the ratio between the 25-point average RMS and the single-point RMS we can define the type of scatter that dominates the phase solution. The analyzed data span a one-year period. The tested GNSS stations belong to the EUREF Permanent Network (EPN) and the International GNSS Service (IGS). These comprise 55 GNSS stations, of which only 23 GNSS stations had more than 95% data availability for the entire year. The RMS and A-RMS are analyzed in conjunction with the precipitable water vapor (PWV), which shows clear signs of temporal correlation. Of the 23 GNSS stations, three stations show an increase of around 50% of the phase RMS when using a 3° cutoff elevation angle, and only four stations have a difference of 5% between the phase RMS when using both cutoff elevation angles. When using the A-RMS, there is an average improvement of 37% of the phase scatter for the 10° cutoff elevation angle, whereas for the 3° cutoff elevation angle, the improvement is around 33%. Based on studying this ratio, four stations indicate that the scatter is dominated by the stronger-than-usual dominance of long-period variations, whereas the others show short-term noise. In terms of station position repeatability, the weighted root mean square (WRMS) is used as an indicator, and the results between the differences of using a 3° and 10° cutoff elevation angle strategy show a difference of −0.16 mm for the North component, −0.21 mm for the East component and a value of −0.75 mm for the Up component, indicating the importance of using optimal cutoff angles.

Dissemination of UTC(NIST) over 20 km of commercial optical fiber with active phase stabilization.

We demonstrate the transfer of a cesium frequency standard steered to UTC(NIST) over 20 km of dark telecom optical fiber. Our dissemination scheme uses an active stabilization technique with a phase-locked voltage-controlled oscillator. Out-of-loop characterization of the optical fiber link performance is done with dual-fiber and single-fiber transfer schemes. We observe a fractional frequency instability of 1.5 × 10-12 and 2 × 10-15 at averaging intervals of 1 s and 105 s, respectively, for the link. Both schemes are sufficient to transfer the cesium clock reference without degrading the signal, with nearly an order of magnitude lower fractional frequency instability than the cesium clocks over all time scales. The simplicity of the two-fiber technique may be useful in future long-distance applications where higher stability requirements are not paramount, as it avoids technical complications involved with the single-fiber scheme.

Impact Analysis of Time Synchronization Error in Airborne Target Tracking Using a Heterogeneous Sensor Network

This paper investigates the influence of time synchronization on sensor fusion and target tracking. As a benchmark, we design a target tracking system based on track-to-track fusion architecture. Heterogeneous sensors detect targets and transmit measurements through a communication network, while local tracking and track fusion are performed in the fusion center to integrate measurements from these sensors into a fused track. The time synchronization error is mathematically modeled, and local time is biased from the reference clock during the holdover phase. The influence of the time synchronization error on target tracking system components such as local association, filtering, and track fusion is discussed. The results demonstrate that an increase in the time synchronization error leads to deteriorating association and filtering performance. In addition, the results of the simulation study validate the impact of the time synchronization error on the sensor network.

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

Current status and applications of time-to-digital converters

Time-to-Digital Converter (TDC) is widely used to realize time interval measurement. The high-precision time measurement technique has important applications in the fields of laser ranging, particle identification, and radioactive nuclear medicine engineering. Based on the existing literature research and data, this paper studies the application areas of TDC in the present development and analyzes the future prospects of TDC applications. The research results showed that: TDC, based on signal screening, realizes time interval measurement as the ultimate purpose of building the system and, at the same time, completes the function of multi-pulse time interval measurement, which can meet the needs of more diversified measurements in the experiments. In the circuit structure, it can identify the feedback output in the all-digital phase-locked loop (ADPLL) and the reference clock phase and frequency information between the feedback output and the reference clock in an ADPLL. It is also promising for use in other areas of high-precision time measurement and processing of circuit signals.

A Proposal for Enhancing Technosignature Search toward the Galactic Center

We discuss the possibility of enhancing intelligent life searches toward the Galactic center. From the clockwork orbital motions of stars around the Sgr A* black hole, we can determine the distance to the Galactic center at an exceptional accuracy, despite its remoteness ∼8.3 kpc. In addition, we can define precise reference epochs by selecting a prominent object such as the bright B-type star S2. These properties have a particular affinity for the coordinated signaling scheme that was hypothesized by Seto for systematically connecting intentional senders to searchers without a prior communication. If S2 is actually being used as a common reference clock, we can compress the search directions around the Galactic center by more than 2 orders of magnitude, with the scanning interval of ∼16 yr.

Robust ambiguity datum for real-time GNSS satellite integer clock estimation

With the capability for single-receiver AR (Ambiguity Resolution), real-time GNSS (Global Navigation Satellite System) satellite integer clock has been the research hotspot of GNSS community in the past decade. Robust ambiguity datum is one prerequisite for high-quality integer clock. In this paper, with undifferenced AR model derived, a robust ambiguity datum definition method is proposed to isolate the signal biases from the integer ambiguity. Firstly, based on the ambiguity graph, the ambiguity datum is selected with the minimum spanning tree algorithm. Secondly, the ambiguity datum is transferred to the subsequent epochs through signal bias connection. Moreover, additional datum ambiguities are introduced to accommodate the arising of receiver and satellite in real-time circumstance. With the combination of ambiguity graph and signal bias, the efficient definition and smooth transition of ambiguity datum are assured for the real-time processing. To validate the approach, simulated real-time integer clock estimation for GPS/Galileo/BDS-3 satellites are conducted with one-month (January 2022) data from about 100 global IGS (International GNSS Service) network stations. Experiments show that the proposed robust ambiguity datum can produce accurate real-time integer clock. The average WL (Wide-Lane) and NL (Narrow-Lane) fixed rates exceed 99 % and 95 %, respectively, for most of the GPS/Galileo satellites. While comparable WL fixed rate is achieved for the BDS-3 satellites, the NL fixed rate is about 5 % lower as a result of poor orbit quality and imperfect measurement model. With eclipsing satellites excluded, the standard deviations between real-time integer clock and post-processed reference clock reach 0.018 ns and 0.016 ns for the GPS and Galileo constellations, respectively, which are 28 % and 24 % smaller than those of corresponding float clocks. In contrast, the standard deviations of float and integer clocks are similar for the BDS-3 constellation. Further improvements on the background models, including unconservative force modeling, satellite attitude modeling and antenna calibration are required to achieve ultimate accuracy, especially for the BDS-3 satellites.

Method of instantaneous signal synchronization of measuring pulse generators

The synchronization methods used in the pulse generators of the G5 measuring group in the external trigger mode are analyzed. The factors determining the error in the formation of time intervals in this mode have been studied. It is shown that the main source of errors in the formation of time intervals during external triggering of measuring pulse generators is the variation in the position of the clock generator reference pulses relative to the external trigger pulses. An analytical review of synchronization methods based on the sampling of time intervals by a multi-tap delay line as a pulse signal propagates along it is carried out. The method of instantaneous synchronization of output pulses is proposed, using sampling of the period of the reference pulses of the clock generator with a multi-tap delay line and fixing the position of the edge of the external trigger pulse within the period of the reference frequency by triggers that control the multiplexer, which connects the output of the multi-tap delay line to the output of the device, at which the edge of the next reference clock pulse generator lags by a minimum time from the front of the external trigger pulse. A device is presented that makes it possible to implement the proposed solution. The simulation of the device was carried out, illustrating the details of its functioning. Jitter was assessed on a prototype device using an integrated 5-tap delay line with a total delay of 20 ns. The method can be applied in measuring pulse generators and belongs to the field of pulse technology.

Research on Implementation of a PWM Generation Algorithm for Train Stationary Stopping Frequency

In industrial electronic equipment or communication equipment, a reference clock should be generated for stable operation of the equipment, which requires precise and stable reference frequency generation. As a method for generating this reference frequency, an analog method called PLL (phase locked-loop) has been devised and widely used. However, in order to make a more precise and stable reference frequency simple and economical, a DDS (direct digital synthesizer) has been developed. In this paper, we propose a stable and accurate method to generate a low frequency of the PWM method via pure logic circuit configuration without a microprocessor for digital reference frequency generation. Depending on the electronic communication equipment, the required reference frequency varies from a low frequency to a very high frequency. The reference frequency synthesis required in these frequency bands has been studied in various ways, but in industries such as railways, the low-frequency band based on the DDS method is used. In particular, it is very important to operate without a single operating error or failure in order to obtain information for stopping the train. Therefore, it is necessary to design a pure logic method that excludes a stored program type processor that minimizes the possibility of temporary interruption due to disturbance such as surge or high voltage. Therefore, through this study, the algorithm is implemented so that the duty ratio is output at 50:50, the circuit is configured so that two target frequencies are generated at the same time, and the performance is verified by generating the low-frequency band used for stopping the railway train. It was confirmed that the accuracy and stability were improved compared to the analog method used for stopping the railway train, and it was verified that the frequency resolution was superior to the similar results obtained in the digital frequency synthesis field so far.

Phase Noise Analysis of Time Transfer over White Rabbit-Network Based Optical Fibre Links.

White Rabbit (WR) is an optical fibre-based time-frequency synchronization technology typically used in timekeeping laboratories for distributing time-frequency signals from a reference clock to distant locations. The accuracy of the received signals at the user end can be affected by random noise processes present in the WR network due to the internal electronic components of WR devices. In this paper, we investigate the presence of random noise processes in the WR network. We then study their statistical properties and model the distribution based on experimentally recorded measurements. According to our study, the probability density function (PDF) follows a Gaussian mixture model (GMM) with varying distribution parameters, and the correlation analysis indicates a strong correlation of the phase noise process over the temporal samples. Furthermore, the developed phase noise models have also been verified by comparing them against additional experimental data. Finally, we present the methodology to generate the phase noise process using computer simulations with the PDF and correlation models developed in this work to help algorithm developers and equipment manufacturers make use of our results.

An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit (FoMjitter) ~−236 dB.

A New Successive Time Balancing Time-to-Digital Conversion Method.

This paper presents a new self-clocked time-to-digital conversion method based on a binary successive approximation (SA) algorithm. Its novelty consists in combining fully clockless operation with direct conversion of the measured time interval. The lack of any reference clock makes the presented method potentially predisposed to low-power solutions. Furthermore, its circuit representation is extremely simple, thereby the ability to direct conversion of time intervals is not burdened by a significant amount of components. The method is intended to measure relatively long time intervals, i.e., hundreds of microseconds. Therefore, it is suitable for e.g., biomedical applications using time-mode signal processing.

A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance

Ring oscillator (RO)-based frequency synthesizers have been widely used in Systems on Chip (SoCs) due to their tiny active area and broad tuning range. However, they also experience significant spur and jitter. Based on an extensive evaluation of the factors of space, power usage, reference clock frequency, jitter, and reference spur. In order to achieve low jitter and low spurious, we present a time-to-voltage conversion phase-locked loop (TVC-PLL) based on a RO in this study. To achieve a wide range of adjustable phase-detection gain, we introduce a time-to-voltage converter (TVC-PD) as a phase detector. We suggest a pre-phase locked module based on orthogonal output clocks help with locking in order to address the problem of the limited phase detection range of conventional TVCs, which can only be used for frequency-locked loops (FLLs). According to simulation results, our suggested TVC-PLL is built using TSMC 65-nm CMOS, uses 4.053 mW of power, and occupies an active area of 0.024 mm2 at a working frequency of 2.4 GHz. It achieves an RMS jitter of 625.4 fs in the 10k to 100MHz frequency range, a reference spur of −77.7 dBc, and a figure-of-merit (FoMJ) of −238.0 dB.

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock frequencies are carefully designed to prevent electromagnetic interference. However, as global navigation satellite system becomes more prevalent, integer-N phase-locked loops face new challenges in generating clocks within the shrinking frequency bands due to large frequency steps determined using a reference clock. To address it, replacing integer-N phase-locked loops with fractional-N phase-locked loops is required. This topic has not been discussed extensively, but it is a practical issue that requires consideration due to its potential impact on development costs. This is why we developed an attachable fractional divider. Our developed divider can efficiently transform integer-N phase-locked loops into fractional-N phase-locked loops, achieving low jitter degradation of 0.35 psrms and a low fractional spur of −69.3 dBc. Thanks to its attachable design, it expedites time-to-market. Regarding mass production, ensuring immunity to process, voltage, and temperature variations is a significant concern. We introduce the circuit techniques employed in the developed fractional divider for immunity to process, voltage, and temperature variations. Subsequently, we provide a comprehensive set of measurement results. The frequency differences over process variations in fractional-N mode is 6.14 ppm. Power supply and temperature dependances are extremely small in spread-spectrum clocking mode. This article illustrates that the developed fractional divider enhances both time-to-market and product reliance.

A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier

ABSTRACT This paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of −77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves −59.7 dBc. It measures the 1.2 s settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 s settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is −105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply.