Reference Capacitor Research Articles

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signal-to-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

Electronically tunable DXCCII-based grounded capacitance multiplier

In this paper a new grounded capacitance multiplier based on DXCCII suitable for operation at low and moderate frequencies is presented. The proposed circuit employs only a single dual-X second-generation current conveyor (DXCCII) active device, used as a voltage amplifier with two NMOS transistors operating in triode region, cooperating with a floating capacitor. The realized equivalent capacitance obtained from Miller multiplication of the reference capacitor and its multiplication factor is electronically tunable. Simulation results using AMS 0.35μm CMOS process technology parameters are included. Functionality of the proposed circuit is verified through its application in a Gm-C second-order low-pass filter.

Current Reference Pre-Charging Techniques for Low-Power Zero-Crossing Pipeline-SAR ADCs

Current pre-charging techniques are introduced to generate the reference in MDACs of pipeline ADCs. They are specifically applied to zero-crossing-based (ZCB) pipeline-SAR ADCs in this paper. The proposed reference pre-charge technique relaxes power and area requirements for reference voltage generation and distribution in ZCB Pipeline ADCs, by eliminating power-hungry low-impedance reference voltage buffers. Dynamic reference loading (DRL), a variant of current reference pre-charging, is further proposed to reduce the loading due to the reference capacitors leading to improvements in the ADC noise performance. A proof-of-principle reference pre-charged DRL ZCB Pipelined-SAR ADC, implemented in 65 nm CMOS, shows an SFDR/SNR/SNDR of 77 dB/70 dB/66 dB at 25 MHz, while consuming 4.8 mW at 50 MS/s for an FOM of 57 fJ/step. The ADC does not require any additional power and/or area for reference voltage generation and distribution.

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alternate comparators clocked asynchronously and a redundant capacitive DAC with constant common mode to improve the accuracy of the comparator. A low-power, clocked capacitive reference buffer is used, and fractional reference voltages are provided to reduce the number of unit capacitors in the capacitive DAC (CDAC). The ADC stacks the CDAC with the reference capacitor to reduce the area and enhance the settling speed. Background calibration of comparator offset is implemented. The ADC consumes 3.1 mW from a 1 V supply and occupies 0.0015 mm2.

High Frequency and Ultrahigh Frequency Radio Frequency Identification Passive Sensor Transponders for Humidity and Temperature Measurement Within Building Structures

This paper presents the development of passive high frequency (HF) and ultrahigh frequency (UHF) radio frequency identification (RFID) sensor transponders for humidity and temperature monitoring. The transponders use RFID integrated circuits with a digital interface for communicating with a ultralow-power microprocessor. The microprocessor handles the measurement, either by charging sensor and reference capacitors, or by commanding a digital sensor. The read ranges of the sensor nodes are 5 cm and up to 40 cm at HF and UHF, respectively. The sensor nodes are demonstrated in concrete casts, where the HF node provides better than 5%RH-repeatability of the moisture measurements from sensor node to another. At UHF the repeatability is about 15%RH.

Influence of domain structure on the nonlinear polarization properties of A 2 BX 4-group crystals

Harmonic analysis of repolarization in A 2 BX 4-group crystals in the ferroelectric phase near phase-transition temperature T c is used to separate the contributions to the harmonic-component amplitudes in the output signal of a Sawyer-Tower circuit from charging the reference capacitor with capacitive and conductive current through such a crystal. Harmonic analysis of dielectric hysteresis loops obtained by placing a specimen in an electric field with harmonically changing strength reveals general regularities in the evolution of the domain walls of A 2 BX 4-group crystals. It is established that the domain structure affects the nonlinear polarization properties of our specimens. The dependence of the potential relief of ferroelectric ion motion in a harmonically changing electric field is plotted on the basis of the experimental results.

Capacitive Sensor Estimation Based on Self-Configurable Reference Capacitance

A number of capacitance readout systems presented in the literature and covered by recent patents are briefly described while a biosensor array readout system developed by the authors is presented in this paper. This biosensor array readout system is based on a charge sensitive amplifier that estimates accurately the difference between a selfconfigurable reference capacitance and a biosensor. In the specific implementation, the self-configurable reference capacitance is automatically configured to a value between 0 and 630pF in steps of 10pF. The configuration of the reference capacitance is controlled by a simple finite state machine that can be implemented using a simple CPLD (Complex Programmable Logic Device) such as Altera EPM7064SLC44-10. The proposed system can be used to measure an absolute biosensor capacitance of up to 640pF with a theoretical sensitivity of 2.5fF. The 2.5fF resolution can be achieved using a low cost/high accuracy 12-bit ADC (Analogue/Digital Converter) like a one that has been described by the authors in a recent patent instead of a 17-bit ADC that would be required to measure the biosensor capacitance value with the same accuracy if a constant 320pF reference capacitor had been used. For this reason, the proposed architecture leads to a lower area/power and higher accuracy implementation compared to a read out circuit that would use a fixed reference capacitance. Although the design of the proposed system was inspired by the development of a biosensor array readout system, a similar architecture can be used by any sensor application that should support a broad capacitive input range with high resolution. Keywords: Biosensor readout, configurable reference capacitors, analogue-to-digital conversion, charge sensitive amplifier, switched capacitance interface.

A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

Improving the Accuracy of Capacitance-to-Frequency Converter by Accumulating Residual Charges

Recently, capacitive sensors, which consist of a sense capacitor and a reference capacitor, have been considered for a sensor array for monitoring biomolecular reactions. Although a capacitance-to-frequency converter (CFC) may be a simple and effective solution for reading a capacitive difference between the sensor capacitors, prior versions lack sufficient accuracy. In this paper, we present a more accurate CFC, which produces a single pulse stream in a wide range of frequencies. This circuit saves residual charges and accumulates them when discharging an integrator capacitor. Implemented in 0.35-μm CMOS technology, our circuit improves the accuracy from about 6% to 0.13 %.

A Deep-Level Transient Spectroscopy Comparison of the SiO2/Si and Al2O3/Si Interface States

Deep Level Transient Spectroscopy (DLTS) has been applied to study the interface states of 5 nm Atomic Layer Deposited (ALD) Al2O3 films on p-type Si. In addition, the passivation of the interface states by Forming Gas Anneal (FGA) and Firing has been explored. It is shown that the near mid-gap density of interface states (Dit) is successfully reduced by both treatments. From a comparison with 5 nm SiO2 reference capacitors it can be concluded that similar interface defects are observed, suggesting that they are dominated by the thin interfacial SiO2 layer formed during ALD.

Effect of the pinning of domain boundaries in Rb2ZnCl4 crystal near the curie point

The contributions to the amplitudes of the harmonic components of the output signal of the Soyer-Tower circuit from charging the reference capacitor with capacitive current and the conduction current of an investigated specimen are separated via the harmonic analysis of repolarization in a Rb2ZnCl4 crystal in the ferroelectric phase near the phase transition temperature T c . Harmonic analysis of the dielectric hysteresis loops obtained when the specimen was affected by an electric field whose intensity E in changed according to harmonic law with amplitude E m showed that at E m > E coer (where E coer is the intensity of the coercive field), the process of repolarization starts and stops when E in reaches values of E m sin(φ0 − α0) and E m sin(φ0 + α0), respectively (where φ0 is the shift of phases between the voltage of the harmonic signal source and the voltage of the first harmonic in the reference capacitor in the Soyer-Tower circuit, and α0 is the phase corresponding to the normalized duration of repolarization). When the current value of intensity E in coincides with E c = E m sinφ0, the direction of polarization reverses. The increase in E c when T c is approached is shown to be the reason for the anomalous temperature-independent behavior of E coer.

A 16-channel capacitance-to-period converter for capacitive sensor applications

An electronic system able to read out arrays of up to sixteen different capacitive type sensors is presented. The output signal of the readout is a square wave signal, with oscillation period linearly modulated by the respective sensor capacitance under measurement. Components such as charge/discharge current control unit, a multiplexing unit and a bandgap voltage reference are integrated on chip, to obtain a stable and linear readout system for multiple sensors of variable types and capacitance ranges. The ASIC was designed and fabricated in AMS 0.35 μm CMOS technology and was hosted on a PCB together with a supervising microcontroller, which is programmed to produce ratiometric measurements using reference capacitances to minimise parasitic effects. Finally, a USB interface undertakes the task of communicating the results to a personal computer. Characterization of the system was performed using (a) discrete capacitances and (b) capacitive pressure sensors. The system was evaluated in a capacitance range of 10---140 pF exhibiting high linearity (r = 0.9954) with sensitivity of 0.062 μs/pF when tested using in-house made capacitive pressure sensors.

A Delta–Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point

We present a low-complexity interface circuit for capacitive sensors that are integrated into sensor microsystems. To reduce hardware cost while keeping high resolution, a first-order delta-sigma modulator (DSM), which balances the charge from the capacitive difference between sense and reference capacitors with the charge from a fixed-quantity capacitor, is employed. A charge-mode digital-to-analog converter and a successive approximation register are utilized to automatically calibrate the zero point of the interface circuit, which may shift further than a dynamic range. A prototype circuit fabricated in a 0.35-μm CMOS process has an active area of 0.048 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Its DSM operates at a sampling frequency of 1 MS/s with an oversampling ratio of 128. Experiments show that this circuit can read a capacitive difference from -0.5 to +0.5 pF with a 0.49-fF resolution. A capacitive offset that causes the zero point to shift can be canceled in the range from -2 to 2 pF with a 31.25-fF resolution. Measured power consumption was 1.44 mW at a 3.3-V supply.

Current-Mode Capacitive Sensor Interface Circuit With Single-Ended to Differential Output Capability

This paper presents a current-mode interface circuit for capacitive sensors, with the main features being its ability to produce a differential output from a single-ended sensor (using a fixed reference capacitor) and its simplicity in realization. These advantages make it a potential candidate for applications where differential sensors are not available and where a simple design is required. The principle is, however, easily applicable to differential sensors as well. The interface concept can be realized in different ways; however, to present a proof of concept on silicon, a prototype has been fabricated and tested in a commercially available 0.8-mum CMOS process. The circuit has been designed using common analog building blocks such as a fully differential operational transconductance amplifier (OTA), a high-output-resistance wide-swing current source, and a single clock phase. The estimated linearity error was 0.2% relative to full-scale swing with a simple two-point calibration. The circuit consumes 145 muA from a 5-V power supply.

A differential capacitive thin film hydrogen sensor

A compact, differential, hydrogen-specific sensor based on the lattice expansion of LaAl 0.3Ni 4.7 metal hydride thin films has been fabricated and characterized. Characterization of LaAl 0.3Ni 4.7 films performed using a capacitance dilatometer revealed that the lattice expansion was proportional to the partial pressure of H 2 over the range 0.01–1.3 atm used in this experiment. The films were mechanically robust to cycling between vacuum and partial pressures of H 2 up to 1.3 atm and were not poisoned by exposure to atmosphere's containing up to 24% carbon monoxide. A wafer level process has been established for the fabrication of the differential hydrogen sensor which includes both an active LaAl 0.3Ni 4.7 sensing capacitor and an inert Au reference capacitor. A minimum sensitivity of 400 ppm hydrogen is calculated for the differential device.

Temperature influence on a differential capacitive rain sensor performances

The temperature influence on the performances of a differential capacitive rain sensor for windows was numerically investigated by Finite Element Method (FEM) before experimental validation. The sensor consists of three coplanar electrodes deposited on a glass substrate defining two capacitors: sensing and reference capacitor. Two types of window glass were used: ordinary and laminated. Despite a significant temperature influence on the capacitances, it turned out that, for sensors made with ordinary glass, the differential mode allows to offset the capacitances variations due to temperature fluctuations and to preserve the effectiveness of the sensor whatever the temperature in the range [−40 °C, +60 °C]. However, in the case of laminated glasses, simulations showed that the differential operating mode was insufficient to completely wipe out the temperature influence on sensor performances because of different temperature dependences of the materials permittivities. In this case, increasing the sensor operating frequency (1 kHz to 100 kHz) resulted in an improved balance of the sensor capacitances while the sensor effectiveness remained preserved.

Practical and simple circuitry for the measurement of small capacitance

Practical and cost-effective circuitry with high sensitivity has been developed to measure a small capacitance using current compensation method. The circuitry uses an electronic switch to periodically connect or separate the capacitor under test (C(x)) from a reference capacitor (C(r)). When C(x) is connected in parallel with C(r) the total capacitance becomes C(x)+C(r). On the other hand, as C(x) is separated from C(r), the total capacitance is only C(r). This periodic change of the capacitance generates a periodic square-wave output with an amplitude in proportion to the capacitance of C(x). A high sensitivity of DeltaV/DeltaC=202.2 mV/pF has been achieved, making the circuitry a powerful tool in measuring small capacitances. Three applications have been performed to present its capability: (a) displacement, (b) height of liquid, and (c) angle of tilt. The experimental results demonstrate the performance of the circuitry.

Low-frequency dielectric measurements of complex fluids using high-frequency coaxial sample cells

A simple and low-cost interface for dielectric measurements with pulsed or time-harmonic excitation is described, covering the frequency range from 30 Hz to 15 MHz. It can be directly connected to the high-frequency coaxial sample cells used for time- or frequency-domain reflectometry (TDR/FDR). Therefore, low-frequency measurements of complex fluids can be made without disturbing the sample. Capacitances from 5 pF to 240 pF are measured with a single set of reference capacitors. One of the reference capacitors is installed as a plug-in element to provide different measurement ranges. A linear substitution technique is described to improve measurement accuracy. The measuring system achieves a standard uncertainty lower than 0.05 pF in the entire frequency range. Experimental results include measurements of lumped capacitors, a coaxial line, a RC circuit, cyclohexane and a ternary microemulsion (water/decane/surfactant).

Configurable electrodes for capacitive-type sensors and chemical sensors

This paper describes a novel design for capacitive sensors or chemical sensors, which features configurable interdigitated electrodes: The electrode spacing can be varied by means of switches on the CMOS chip. This new design allows for performing two capacitive measurements with one single-sensor capacitor so that the number of sensors required to acquire a certain amount of information can be significantly reduced. The use of the same sensor and the same polymer layer for two measurements at a different electrode periodicity provides a better signal quality for the difference signal since detrimental influences, such as humidity and sensor drift, are similar for both electrode configurations and are strongly correlated. Such high signal quality is required for, e.g., the successful recognition of n-octane in the presence of tenfold larger background signals of humidity or, in general, for the determination of low analyte concentrations in humid air. The baseline drift in the concentration predictions based on the differential signal from the two electrode configurations was an order of magnitude lower than that for uncorrelated signals produced by two separate interdigitated capacitors on the same chip. Since the number of required sensors is reduced and, owing to the differential readout of two electrode configurations, reference capacitors are no longer necessary, the overall chip size and/or the number of sensor chips and, consequently, costs can be considerably reduced.

A High-Frequency Nonquasi-Static Analytical Model Including Gate Leakage Effects for On-Chip Decoupling Capacitors

This paper presents a compact model for on-chip decoupling capacitors (decaps) including gate-oxide leakage. The model makes use of only four parameters, namely, channel resistance, gate-oxide capacitance, and two parameters to quantify gate-oxide leakage, to predict the static and dynamic response of decaps. Quality indices have been defined to enable development of decap design guidelines and evaluation of performance of such capacitors. The model shows how the gate leakage and longer channel lengths severely affect the performance of on-chip decaps for both low and high frequencies. The model also shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. Application of the model uncovers tradeoffs for thin- and thick-oxide capacitors in an available 90-nm CMOS technology. For a general-purpose technology, a reference capacitance value has been realized using decaps with a discrete width and length. Our model predicts that thick-oxide n-channel (p-channel) capacitors require /spl sim/3.37x (/spl sim/3.31x) more silicon area and /spl sim/1.70x (/spl sim/1.17x) degraded time response as compared to their thin-oxide versions. The time response is even more degraded (/spl prop/L/sup 2/) when longer channel decaps are used. This paper contributes by defining performance benchmarks for decaps.