Redundant Load Research Articles

Rehabilitation of apartial maxillectomy patient with silicone relined hollow bulb obturator – Case report

Maxillary resection results in a discontinuity of the oral nasal and maxillary sinus cavities. Defect of any extent results in significant disabilities experienced by the patient. This may be manifested as difficulties in speech, mastication and esthetics.Prosthetic rehabilitation in the form of a palatal obturator is usually required to cover the defect and restore normal functions. In the cases of edentulous patients application of anobturator becomes even more cumbersome as the mechanism of retention is compromised.Achieving peripheral seal is questionable. In the present case, palatal defect is rehabilitated with silicone relined hollow bulb obturator. The portrayed obturator reduces the redundant load on the supporting tissue and provides a functional solution to the compromised state of the patient.

ISwitch

Large-scale computing systems such as data centers are facing increasing pressure to cap their carbon footprint. Integrating emerging clean energy solutions into computer system design therefore gains great significance in the green computing era. While some pioneering work on tracking variable power budget show promising energy efficiency, they are not suitable for data centers due to lack of performance guarantee when renewable generation is low and fluctuant. In addition, our characterization of wind power behavior reveals that data centers designed to track the intermittent renewable power incur up to 4X performance loss due to inefficient and redundant load matching activities. As a result, mitigating operational overhead while still maintaining desired energy utilization becomes the most significant challenge in managing server clusters on intermittent renewable energy generation. In this paper we take a first step in digging into the operational overhead of renewable energy powered data center. We propose iSwitch, a lightweight server power management that follows renewable power variation characteristics, leverages existing system infrastructures, and applies supply/load cooperative scheme to mitigate the performance overhead. Comparing with state-of-the-art renewable energy driven system design, iSwitch could mitigate average network traffic by 75%, peak network traffic by 95%, and reduce 80% job waiting time while still maintaining 96% renewable energy utilization. We expect that our work can help computer architects make informed decisions on sustainable and high-performance system design.

An efficient handover decision method based on frame retransmission and data rate for multi-rate WLANs

To enhance the communication performance at handover between multi-rate WLANs, we propose a new handover decision method that can be applied to our previously reported handover management scheme, which handled a handover by utilizing two WLAN interfaces (IFs) through cross-layer collaboration between layer 2 and layer 4. It should be noted that we here propose a new handover decision scheme for traversing between multi-rate WLANs, while our previous decision scheme works only in fixed-rate WLANs. In this paper, to treat a handover between multi-rate WLANs, we employ two kinds of information: (1) the most frequently used data rate (MFDR) for assessing the stable communication performance of a multi-rate WLAN, and (2) the frame retransmission ratio (FRR) for assessing its exact communication performance. The MFDR enables us to estimate the area where we should start handover. If the MFDRs of two interfaces are same in the area, the FRR allows us to compare the wireless condition on the two interfaces precisely to give an optimal handover point. Through simulation experiments, we show that our proposed scheme certainly estimates an appropriate handover point as a result of multi-path transmission (s), thereby providing handover successfully. That is, the proposed method can determine handover at an optimal point depending on the various distances between access points, the mobile node (MN) velocity, and the MN moving pattern. Moreover, our proposed scheme prevents the redundant network load caused by multi-path transmission as much as possible, thereby providing the ideal TCP communication performance.

Basic Principal and Design Methodology of Progressive Storey Collapse Resistance in a New Type RC Twin-Frame Structure

According to earthquake hazard, normal frame structures could hardly avoid failure of ‘Strong Beam and Weak Column’, weak layer and even progressive storey collapse under strong earthquakes, a main reason is the lack of second seismic fortification line in frame structure. Based on the design thought of multiple seismic fortification lines, reinforced concrete twin-frame structure is initiated in this paper. Major feature is increases of redundant constraints and load paths due to added outer limb-columns could take effect as the second seismic fortification line. Twin-frame structure could not only fulfill the demand of ‘three levels, two stages’ in seismic code, but also have been designed through the third stage of ‘resist progressive collapse’, using key member method to promote safety storage and deformability of outer limb-columns, using removal key member method to verify vertical ultimate load of frame beams in weak layer. Though twin-frame structure could not completely avoid plastic hinges in column ends, progressive storey collapse will not appear in this kind of structure. Twin-frame structure is a new structure system which could be applied in constituting new projects as well as strengthening and rebuilding existing projects, further research can be done on this structure system.

On the Analysis and Design of Steel Structure to Mitigate Progressive Collapse

Since Ronan Point tower local collapse in UK in 1968, progressive collapse phenomenon in structures attracted more attention for civil engineers all over the world so there were no useful researches and manual codes related to progressive collapse designing before. Progressive collapse occurs when loading pattern, boundary condition and resisting path changed, so critical elements undergo excessive unpredicted loading. We cannot omit reason of collapse as well as prevention of distribution of it that cause progressive collapse. Also, we cannot predict exact location of collapse beginning, so we should generalized design guides to whole or part of structures elements based on risk analyzing. Also we can use load carrying element removal scenario for critical elements. To prevent progressive collapse, structural systems require to having a well-distributed, redundant lateral load resisting system and ductile connections capable of undergoing large inelastic rotations without failing. There are some new guides and criteria for elements and connections to be designed to resist progressive collapse. Depends on required accuracy, importance of the buildings and acceptable risk level, the analysis methodologies ranged from linear to nonlinear with static and dynamic approaches. In this paper, codes and researches recommendations to resist progressive collapse for steel structures are presented, classified and compared. Also, applicable design methods based on codes and some retrofitting methods are summarized.

On Reducing Hidden Redundant Memory Accesses for DSP Applications

Reducing memory accesses is particularly important for digital signal processing (DSP) applications since they are widely used in embedded systems and need to be executed with high performance and low power consumption. In this paper, we propose a machine-independent loop memory access optimization technique, redundant load exploration and migration (REALM), to explore hidden redundant load operations and migrate them outside loops based on loop-carried data dependence analysis. We implement REALM into IMPACT and Trimaran. To the best of our knowledge, this is the first work to implement the memory access reduction with loop-carried data reuse in real world compilers. We conduct experiments using a set of benchmarks from DSPstone and MiBench on the cycle-accurate VLIW simulator of Trimaran. The experimental results show that our technique significantly reduces the number of memory accesses.

Analytical Investigation of the Toughening Potential of a Failure Tailoring Concept

A parametric study has been performed to determine the upper bounds of toughening benefit achievable using an approximate model for the response of one-dimensional, tailored, flexible composite-material tethers with progressive failure. The tailoring concept is achieved through judicious arrangement of redundant load paths with unequal length and strength and has been proposed, modeled, and experimentally verified in previous research. The model is recast in this work using nondimensional material-independent parameters that are varied over ranges of interest in advanced composites. The effects of each parameter on the response of the tailored member are discussed. An increase of nearly two orders of magnitude in toughness over an untailored member is found to be attainable by taking complete advantage of the energy dissipated by the failure of each load path within the bounds of the study. Challenges to implementation of the tailored member as approximated by the model are also discussed.

Generalised singular value decomposition-based algorithm for multi-user multiple-input multiple-output linear precoding and antenna selection

Multi-user multiple-input multiple-output (MU-MIMO) linear precoding utilising generalised singular value decomposition (GSVD) is proposed. The authors precoding scheme maximises the signal-to-leakage and noise ratio (SLNR), so that it does not require any iteration to obtain precoding/decoding matrices, a feature that distinguishes it from previous signal to interference and noise ratio (SINR) maximising precoding schemes. The SLNR maximising precoding weight may be obtained by the generalised eigenvalue decomposition (GEVD). However, the covariance matrix whose GEVD is computed becomes near singular as the signal-to-noise ratio goes high. To overcome this numerical problem, the proposed precoding scheme avoids any matrix inversion and matrix ‘squaring’ operations, removing redundant computational loads, and consequently saves computational resources and improves numerical accuracy. To further improve the system performance, an efficient antenna selection scheme using the GSVD is also proposed. The scheme does not require an exhaustive search to choose an active antenna set.

A Dynamic Web Caching Technique for using 'URL Rewriting'

In order to make surfing the internet faster, and to save redundant processing load with each request for the same web page, many caching techniques have been developed to reduce latency of retrieving data on World Wide Web. In this paper we will give a quick overview of existing web caching techniques used for dynamic web pages then we will introduce a design and implementation model that take advantage of “URL Rewriting” feature in some popular web servers, e.g. Apache, to provide an effective approach of caching dynamic web pages.

Energy-Dissipating Composite Members with Progressive Failure: Impulsive Response and Experimental Verification

An experimental investigation of response for tailored one-dimensional energy-dissipating composite members with progressive failure subject to quasi-static and impulsive tensile loading is presented. The tailoring concept relies upon a progressive failure sequence of redundant load paths of tailored strength and length to induce a yield-type response. In a prior publication the authors presented the concept development and analytical modeling of response under quasi-static loading. In this paper, an experimental verification is provided using a universal testing machine for members under quasi-static uniaxial loading. Furthermore, the model is extended to impulsive loading, and a custom-design drop test setup is developed to provide an experimental validation of analytical response. The results obtained confirm the hypothesized progressive failure sequence of redundant load paths, thereby validating the failure tailoring concept, as well as the accuracy and predictive power of the developed models of response in terms of both the number of partial failures induced for a given loading and the increased energy dissipation capability. Potential aerospace applications include snap-resistant tensile structures, for example space tethers, towing and cargo restraint lines, crashworthy helicopter troop seat stroke control straps, and aircraft emergency arrest gear.

Acceleration of Market Value-at-Risk Estimation

The proliferation of algorithmic trading, derivative usage and highly leveraged hedge funds necessitates the acceleration of market Value-at-Risk (VaR) estimation to measure the severity of portfolios losses. This paper demonstrates how solely relying on advances in computer hardware to accelerate market VaR estimation overlooks significant opportunities for acceleration. We use a simulation based delta-gamma Value-at-Risk (VaR) estimate and compute the loss function using basic linear algebra subroutines (BLAS). Our NVIDIA GeForce GTX280 graphics processing unit (GPU) based baseline implementation is a straight-forward port from the CPU implementation and only had a 8.21x speed advantage over a quad-core Intel Core2 Q9300 central processing unit (CPU) based implementation.We demonstrate three approaches to gain additional speedup over the baseline GPU implementation. Firstly, we reformulate the loss function to reduce the amount of necessary computation and achieved a 60.3x speedup. Secondly, we selected functionally equivalent distribution conversion modules to give the best convergence rate - providing an additional 2x speedup. Thirdly, we merged data-parallel computational kernels to remove redundant load store operations leading to an additional 1.85x speedup. Overall, we have achieved a speedup of 148x against the baseline GPU implementation, reducing the time of a VaR estimation with a standard error of 0.1% from minutes to less than one second.

Multi-perspective performance reporting and organisational performance: the impact of information, data and redundant cue load

Multi-perspective performance reporting systems (MPRS), such as the balanced scorecard (BSC), have become popular. The BSC reports performance about four perspectives (learning and growth, internal business processes, customer and financials). Although these systems are important, research in these areas has only just scratched the surface, hence the motivation for this study. A possible problem with multi-perspective systems is that they may cause information/data/redundant cue (I/D/C) overload and thus detrimentally affect the performance. The objectives of this research are to: (1) explore the relationship between MPRS and organisational performance and (2) study the relationship between I/D/C load and organisational performance in multi-perspective systems. We found that (1) MPRS are positively associated with performance and (2) there is a weak negative association between I/D/C overload and performance. Our exploratory results are consistent with the views of advocates of MPRS (e.g. Kaplan and Norton) that MPRS enhance organisational performance.

A Design and Implementation Model for Web Caching Using Server "URL Rewriting"

Abstract — In order to make surfing the internet faster, and to save redundant processing load with each request for the same web page, many caching techniques have been developed to reduce latency of retrieving data on World Wide Web. In this paper we will give a quick overview of existing web caching techniques used for dynamic web pages then we will introduce a design and implementation model that take advantage of “URL Rewriting” feature in some popular web servers, e.g. Apache, to provide an effective approach of caching dynamic web pages. Keywords — Web Caching, URL Rewriting, Optimizing Web Performance, Dynamic Web Pages Loading Time. I. I NTRODUCTION BOUT two decades ago, most of web pages on the internet were just static HTML pages and the job of building a website was an easy job and doesn’t require much knowledge of computer programming. But nowadays most of websites are dynamic ones which rely on a scripting language to run, and become more complicated as they provide new features such as personalization of contents and dynamic advertisements. Also it allows just about anyone, with limited or no web design experience, to update their own website via an administrative backend [7]. But unfortunately loading of a web dynamic page is slower and requires more operations than loading a static page [14], [15]. As a result the need of web caching becomes crucial as dynamic pages are the dominant in the web. To alleviate server processing overhead and reduce loading time of dynamic web page, it is possible to get the generated output of the dynamic page and save it in the cache, so that any subsequent request will be served from the cache only with no need to execute the same code again [12], [13]. Thus a dynamic web page can be served nearly as a static one. In this paper we will discuss the popular techniques of web caching used today, and then we will introduce a simple de-sign model and its implementation of a web caching technique followed by a comparison study and an analysis of the enhanced performance after using this technique.

Virtual machine showdown

Virtual machines (VMs) enable the distribution of programs in an architecture-neutral format, which can easily be interpreted or compiled. A long-running question in the design of VMs is whether a stack architecture or register architecture can be implemented more efficiently with an interpreter. We extend existing work on comparing virtual stack and virtual register architectures in three ways. First, our translation from stack to register code and optimization are much more sophisticated. The result is that we eliminate an average of more than 46% of executed VM instructions, with the bytecode size of the register machine being only 26% larger than that of the corresponding stack one. Second, we present a fully functional virtual-register implementation of the Java virtual machine (JVM), which supports Intel, AMD64, PowerPC and Alpha processors. This register VM supports inline-threaded, direct-threaded, token-threaded, and switch dispatch. Third, we present experimental results on a range of additional optimizations such as register allocation and elimination of redundant heap loads. On the AMD64 architecture the register machine using switch dispatch achieves an average speedup of 1.48 over the corresponding stack machine. Even using the more efficient inline-threaded dispatch, the register VM achieves a speedup of 1.15 over the equivalent stack-based VM.

Interprocedural side-effect analysis for incomplete object-oriented software modules

We introduce a new approach to computing interprocedural modification side effects for part of an object-oriented program (e.g., components, libraries or client modules). Our approach consists of first performing a whole-program points-to analysis to such an incomplete program and then applying a so-called mutability analysis (MA) to determine which objects in the program are mutable by unknown code and which references and call sites in the program are complete (since their points-to sets and target methods are statically resolvable). Based on these results, we present a new MA-based interprocedural side-effect analysis for computing the modification side-effects for an incomplete program. Our experimental results show that our mutability analysis enables a variety of pure methods to be detected, yielding the purity information useful in program understanding and debugging. In addition, our MA-based side-effect analysis enables more redundant loads to be removed than a recent TBAA-based PRE algorithm guided by type-based alias analysis (TBAA). Our approach is simple since it is flow-insensitive and achieves these improvements at small costs.

An Adaptive Failure Detector for Grid Based on QoS

Failure detector is one of the fundamental building blocks to build reliable grid environments. There are large numbers of distributed applications with different QoS of failure detection in grids. Thus, in order to keep its efficiency and scalability in grid environments, a failure detector should not only provide QoS of accurate failure detection for applications, but also avoid redundant loads of designing multiple detectors for different QoS. Therefore, a new failure detector GA-FD (adaptive failure detector for grid) is presented, which adopts heartbeat detection strategy based on PULL mode. GA-FD can provide QoS of failure detection for multi-applications according to quantitative QoS metrics , and does not need any hypothesis about message behavior ) , , (

Continuous Optimization

This paper presents a hardware-based dynamic optimizer that continuously optimizes an applicationýs instruction stream. In continuous optimization, dataflow optimizations are performed using simple, table-based hardware placed in the rename stage of the processor pipeline. The continuous optimizer reduces dataflow height by performing constant propagation, reassociation, redundant load elimination, store forwarding, and silent store removal. To enhance the impact of the optimizations, the optimizer integrates values generated by the execution units back into the optimization process. Continuous optimization allows instructions with input values known at optimization time to be executed in the optimizer, leaving less work for the out-of-order portion of the pipeline. Continuous optimization can detect branch mispredictions earlier and thus reduce the misprediction penalty. In this paper, we present a detailed description of a hardware optimizer and evaluate it in the context of a contemporary microarchitecture running current workloads. Our analysis of SPECint, SPECfp, and mediabench workloads reveals that a hardware optimizer can directly execute 33% of instructions, resolve 29% of mispredicted branches, and generate addresses for 76% of memory operations. These positive effects combine to provide speed ups in the range 0.99 to 1.27.

Store Vulnerability Window (SVW)

The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques use some form of speculation to simplify the load-store unit and check this speculation by re-executing some of the loads prior to commit. We call such techniques load optimizations. One recent load optimization improves load queue (LQ) scalability by using re-execution rather than associative search to check speculative intra- and inter- thread memory ordering. A second technique improves store queue (SQ) scalability by speculatively filtering some load accesses and some store entries from it and re-executing loads to check that speculation. A third technique speculatively removes redundant loads from the execution engine; re-execution detects false eliminations. Unfortunately, the benefits of a load optimization are often mitigated by re-execution itself. Re-execution contends for cache bandwidth with store commit, and serializes load re-execution with subsequent store commit. If a given load optimization requires a sufficient number of load re-executions, the aggregate re-execution cost may overwhelm the benefits of the technique entirely and even cause drastic slowdowns. Store Vulnerability Window (SVW) is a new mechanism that significantly reduces the re-execution requirements of a given load optimization. SVW is based on monotonic store sequence numbering and an adaptation of Bloom filtering. The cost of a typical SVW implementation is a 1KB buffer and a 16-bit field per LQ entry. Across the three optimizations we study, SVW reduces re-executions by an average of 85%. This reduction relieves cache port contention and removes many of the dynamic serialization events that contribute the bulk of re-executionýs cost, allows these load optimizations to perform up to their full potential. For the speculative SQ, this means the chance to perform at all, as without SVW it posts significant slowdowns.

Automated soundness proofs for dataflow analyses and transformations via local rules

We present Rhodium, a new language for writing compiler optimizations that can be automatically proved sound. Unlike our previous work on Cobalt, Rhodium expresses optimizations using explicit dataflow facts manipulated by local propagation and transformation rules. This new style allows Rhodium optimizations to be mutually recursively defined, to be automatically composed, to be interpreted in both flow-sensitive and -insensitive ways, and to be applied interprocedurally given a separate context-sensitivity strategy, all while retaining soundness. Rhodium also supports infinite analysis domains while guaranteeing termination of analysis. We have implemented a soundness checker for Rhodium and have specified and automatically proven the soundness of all of Cobalt's optimizations plus a variety of optimizations not expressible in Cobalt, including Andersen's points-to analysis, arithmetic-invariant detection, loop-induction-variable strength reduction, and redundant array load elimination.

Compiler transformations for effectively exploiting a zero overhead loop buffer

A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequence of instructions that will be executed a specified number of times without incurring any loop overhead. Unlike loop unrolling, a loop buffer can be used to minimize loop overhead without the penalty of increasing code size. In addition, a ZOLB requires relatively little space and power, which are both important considerations for most DSP applications. This paper describes strategies for generating code to effectively use a ZOLB. We have found that many common code improving transformations used by optimizing compiler on conventional architectures can be easily used to (1) allow more loops to be placed in a ZOLB, (2) further reduce loop overhead of the loops placed in a ZOLB, and (3) avoid redundant loading of ZOLB loops. The results given in this paper demonstrate that this architectural feature can often be exploited with substantial improvements in execution time and slight reductions in code size for various signal processing applications.