Redundant Binary Research Articles

A Scalable Montgomery Modular Multiplication Architecture with Low Area-Time Product Based on Redundant Binary Representation

The Montgomery modular multiplication is an integral operation unit in the public key cryptographic algorithm system. Previous work achieved good performance at low input widths by combining Redundant Binary Representation (RBR) with Montgomery modular multiplication, but it is difficult to strike a good balance between area and time as input bit widths increase. To solve this problem, based on the redundant Montgomery modular multiplication, in this paper, we propose a flexible and pipeline hardware implementation of the Montgomery modular multiplication. Our proposed structure guarantees a single-cycle delay between two-stage pipeline units and reduces the length of the critical path by redistributing the data paths between the pipelines and preprocessing the input in the loop. By analyzing the structure and comparing the related work in this paper, our structure ensures a lower area-time product while achieving a controllable and small area consumption. The comprehensive results under different Taiwan Semiconductor Manufacturing Company (TSMC) processes demonstrate the advantages of our structure in terms of flexibility and area-time product.

Design and implementation of fast RBSD multiplier

In the developing world, we need to meet the high-speed requirements of users in chips. It has become a necessity to have faster and more efficient gadgets in all sectors which can work beyond our expectations and imaginations and give a better experience. So, for that we have designed a multiplier which is faster and can provide results precisely. In this paper we are using RBSD encodings which make multiplier faster by not doing carry propagations and thereby reducing delay for getting output. Redundant Binary Signed Decimals (RBSD) multipliers are designed in such a way that it reduces partial products in multiplication and thereby the multiplier is carry-free. The RBSD multiplier proposed in this paper can perform both signed and unsigned number multiplication. The proposed system is being implemented in VIVADO 2020.2 version in Verilog language. This paper is a comparative analysis with the existing model of RBSD multiplier.

A High-Performance and Low-Cost Montgomery Modular Multiplication Based on Redundant Binary Representation

In this brief, Redundant Binary Representation (RBR) is applied in Montgomery modular multiplication (MMM) to eliminate the long carry chain and realize parallel computation. A novel MMM algorithm based on RBR is proposed. Based on the proposed algorithm, different sizes of high-performance and low-cost Montgomery multipliers are implemented in TSMC CMOS process technology. The experimental results demonstrate that our design has significant advantages in terms of performance, area and Area-Time-Product over previous researches. It’s worth mentioning that our 8192-bit Montgomery multiplier (TMSC 65nm) with 603MHz working frequency and 878.1K equivalent gates can complete the MMM in only 3403ns.

Design and Analysis of Multipliers using Radix-8 Booth Encoding Technique for Low Power and Area Consumption

As innovation scaling is arriving at its points of confinement, new methodologies have been proposed for computational efficiency. Different techniques have been proposed with advancements in technology to model high-speed along with low power consumption and smaller area multipliers. For the radix-4 booth propagation algorithm for low-power and low complexity applications, an efficient approximate 8 bit redundant multiplier is used. To minimize the complication present in modified booth encoder, approximate Booth RB encoders have been introduced by modifying the truth table with incorrect bits, which resulted in a reduction of the power delay product. Approximate computing is a relevant technique for low power and high performance circuits as used in error-tolerant applications. Approximate or inexact computing is an attractive design methodology for low power design but accomplished by loosening up the necessity of precision. It becomes critical to maintain full accuracy to attain reduced power utilization. In this paper, the design of approximate redundant binary (RB) multipliers is studied and modified to build less complex multiplier with Radix-8 modified booth encoding technique to reduce area and complexities of architectures.

Design and Analysis of Approximate Redundant Binary Multipliers

As technology scaling is reaching its limits, new approaches have been proposed for computional efficiency. Approximate computing is a promising technique for high performance and low power circuits as used in error-tolerant applications. Among approximate circuits, approximate arithmetic designs have attracted significant research interest. In this paper, the design of approximate redundant binary (RB) multipliers is studied. Two approximate Booth encoders and two RB 4:2 compressors based on RB (full and half) adders are proposed for the RB multipliers. The approximate design of the RB-Normal Binary (NB) converter in the RB multiplier is also studied by considering the error characteristics of both the approximate Booth encoders and the RB compressors. Both approximate and exact regular partial product arrays are used in the approximate RB multipliers to meet different accuracy requirements. Error analysis and hardware simulation results are provided. The proposed approximate RB multipliers are compared with previous approximate Booth multipliers; the results show that the approximate RB multipliers are better than approximate NB Booth multipliers especially when the word size is large. Case studies of error-resilient applications are also presented to show the validity of the proposed designs.

An efficient redundant binary adder with revised computational rules

Redundant binary representation (RBR) offers a carry-free addition of two redundant binary (RB) numbers. The computational rules of the conventional RB adder (CRBA) generate intermediate sum and carry vectors in RBR, leads to area overhead and pre-hardware elements for reverse conversion (RC). We have considered that the intermixing of inverted encoding of negabits (IEN) representation and conventional binary bits or posibits can be realized using standard hardware blocks. This paper provides a new computational rule for RB adder generating the intermediate sum and intermediate carry in posibit and IEN representations replacing the redundant digits. Thus, the proposed RB adder provides a single stage RB adder omitting the requirement of intermediate RB digits. For circuit synthesis of the proposed designs, we have considered Encounter® RTL Compiler and Xilinx Synthesis Technology in ASIC and FPGA platforms respectively. The comparative study of proposed NRBA offers improved design parameters as compared to CRBA.

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

Time efficient signed Vedic multiplier using redundant binary representation

This study presents a high-speed signed Vedic multiplier (SVM) architecture using redundant binary (RB) representation in Urdhva Tiryagbhyam (UT) sutra. This is the first ever effort towards extension of Vedic algorithms to the signed numbers. The proposed multiplier architecture solves the carry propagation issue in UT sutra, as carry free addition is possible in RB representation. The proposed design is coded in VHDL and synthesised in Xilinx ISE 14.4 of various FPGA devices. The proposed SVM architecture has better speed performances as compared with various state-of-the-art conventional as well as Vedic architectures.

New insights on neutral binary representations for evolutionary optimization

This paper studies a family of redundant binary representations NNg(ℓ,k), which are based on the mathematical formulation of error control codes, in particular, on linear block codes, which are used to add redundancy and neutrality to the representations. The analysis of the properties of uniformity, connectivity, synonymity, locality and topology of the NNg(ℓ,k) representations is presented, as well as the way an (1+1)-ES can be modeled using Markov chains and applied to NK fitness landscapes with adjacent neighborhood.The results show that it is possible to design synonymously redundant representations that allow an increase of the connectivity between phenotypes. For easy problems, synonymously NNg(ℓ,k) representations, with high locality, and where it is not necessary to present high values of connectivity are the most suitable for an efficient evolutionary search. On the contrary, for difficult problems, NNg(ℓ,k) representations with low locality, which present connectivity between intermediate to high and with intermediate values of synonymity are the best ones. These results allow to conclude that NNg(ℓ,k) representations with better performance in NK fitness landscapes with adjacent neighborhood do not exhibit extreme values of any of the properties commonly considered in the literature of evolutionary computation. This conclusion is contrary to what one would expect when taking into account the literature recommendations. This may help understand the current difficulty to formulate redundant representations, which are proven to be successful in evolutionary computation.

A Modified Partial Product Generator for Redundant Binary Multipliers

Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage. Therefore, the proposed RBMPPG generates fewer partial product rows than a conventional RB MBE multiplier. Simulation results show that the proposed RBMPPG based designs significantly improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits; these reductions over previous NB multiplier designs incur in a modest delay increase (approximately 5 percent). The power-delay product can be reduced by up to 59 percent using the proposed RB multipliers when compared with existing RB multipliers.

CRBBE ALGORITHM FOR LOW POWER AND HIGH SPEED MULTIPLIER DESIGN

With the advent of the VLSI technology, designers could design simple chips with the more number of transistors. multipliers have large area, long latency and consume considerable power. Reduction of power consumption makes a device reliable. and The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition, a high-radix-modified booth encoding algorithm is desired. However its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary(NB) to RB conversion. This paper proposes new RB booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent booth encoded digits to directly from an RB partial product to avoid the hard multiple of high-radix booth encoding without incurring any correction vector, and the algorithm achieved high speed compared to existing multiplication algorithms for a gamut of power –of-to word lengths up to 64 b.

A Study of Redundancy and Neutrality in Evolutionary Optimization

Some authors consider that evolutionary search may be positively influenced by the use of redundant representations, whereas others note that the addition of random redundancy to a representation could be useless in optimization. Given this lack of consensus, two new families of redundant binary representations are developed in this paper. The first family is based on linear transformations and is considered non-neutral. The second family of representations is designed to implement neutrality, and is based on the mathematical formulation of error control codes. A study aimed at assessing the influence of redundancy and neutrality on the performance of a simple evolutionary hillclimber is presented. The (1+1)-ES is modeled using Markov chains and is applied to NK fitness landscapes. The results indicate that the phenotypic neighborhood induced by a redundant representation dominates the behavior of the algorithm, affecting the search more strongly than neutrality, and the representations with better performance on NK fitness landscapes do not exhibit extreme values of any of the indicators of representation quality commonly adopted in the literature.

Correcting the Normalization Shift of Redundant Binary Representations

An important problem in the realization of floating-point subtraction is the identification of the position of the first nonzero digit in a radix-represented number, since the significand usually is to be represented left-normalized in the part of the word(s) allocated for representing its value. There are well-known log-time algorithms for determining this position for numbers in nonredundant representations, which may also be applied to suitably (linear-time) transformed redundant representations. However, due to the redundancy in the latter case, the position thus determined may need a correction by one. When determination of the shift amount is to be performed in parallel with conversion to nonredundant representation (the subtraction), it must be performed on the redundant representation. This is also the case when the significand is to be retained in a redundant representation until the final rounding. This paper presents an improved algorithm for determining the need for a correction of the normalization shift amount, which can be run in parallel with the algorithm finding the approximate position.

A Novel Redundant Binary Number to Natural Binary Number Converter

Redundant binary number appears to be appropriate for high-speed arithmetic operation, but the delay and hardware cost associated with the conversion from redundant binary (RB) to natural binary (NB) number is still a challenging task. In the present investigation a simple approach has been adopted to achieve high speed with lesser hardware and power saving. A circuit level approach has been adopted to implement the equivalent bit conversion algorithm (EBCA) (Kim et al. IEEE Journal of Solid State Circuits 36:1538-1544, 2001, 38:159-160, 2003) for RB to NB conversion. The circuit is designed based on exploration of predictable carry out feature of EBCA algorithm. This implementation concludes a significant delay power product and component complexity advantage for a 64-bit RB to NB conversion using novel carry-look-ahead equivalent bit converter.

A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired. However, its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary (NB) to RB number conversion. This paper proposes a new RB Booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent Booth encoded digits to directly form an RB partial product to avoid the hard multiple of high-radix Booth encoding without incurring any correction vector. The proposed method leads to lower encoding and decoding complexity than the recently proposed RB Booth encoder. Synthesis results using Artisan TSMC 0.18-mum standard-cell library show that the RB multipliers designed with our proposed Booth encoding algorithm exhibit on average 14% higher speed and 17% less energy-delay product than the existing multiplication algorithms for a gamut of power-of-two word lengths from 8 to 64 b.

A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams

This paper introduces a systematic approach to designing high-performance parallel adders based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with word-level operands, whereas a low-level CTD represents a network of primitive components that can be directly mapped onto physical devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs in a formal manner. In this paper, we focus on an application of CTDs to the design of redundant arithmetic adders with limited carry propagation. For any redundant number representation, we can obtain the optimal adder structure by trying every possible CTD decomposition and CTD-variable encoding. The potential of the proposed approach is demonstrated through an experimental synthesis of Redundant-Binary (RB) adders with CMOS standard cell libraries. We can successfully obtain RB adders that achieve an about 30-40% improvement in terms of power-delay product compared with conventional designs.

A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter

This paper presents an efficient reverse converter for transforming the redundant binary (RB) representation into two's complement form. The hierarchical expansion of the carry equation for the reverse conversion algorithm creates a regular multilevel structure, from which a high-speed hybrid carry-lookahead/carry-select (CLA/CSL) architecture is proposed to fully exploit the redundancy of RB encoding for VLSI efficient implementation. The optimally designed CSL sections interleaved evenly in the mixed-radix CLA network to boost the performance of the reverse converter well above those designed based on a homogeneous type of carry propagation adder. The logical effort characterization captures the effect of circuit's fan-in, fan-out and transistor sizing on performance, and the evaluation shows that our proposed architecture leads to the fastest design. A 64-bit transistor-level circuit implementation of our proposed reverse converter and that of its most competitive contender were simulated to validate the logical effort delay model. The pre- and post-layout HSPICE simulation results reveal that our new converter expends at least two times less energy (power-delay product) than the competitor circuit and is capable of completing a 64-bit conversion in 829 ps and dissipates merely 5.84 mW at a data rate of 1 GHz and a supply voltage of 1.8 V in TSMC 0.18-mum CMOS technology.

Super-high Speed, Accuracy, and Modularized Residue Number System based on Redundant Binary Representation

Super-high Speed, Accuracy, and Modularized Residue Number System based on Redundant Binary Representation

A carry-free 54b×54b multiplier using equivalent bit conversion algorithm

An equivalent bit conversion algorithm (EBCA) is proposed to eliminate the need for final carry propagation in the redundant binary (RB) to normal binary (NB) conversion step for RB multiplication. The multiplication process helps with the carry-free conversion step by eliminating certain combinations of RB product. When the EBCA is applied, conventional power-consuming carry-propagating adders are replaced by simple, minimum-sized carry-free converters, and the entire multiplication process can be made free of carry propagation from input to output. The method employed in this work reduces 40% of the total power and 30% of the total multiplication time in the final adder stage of traditional multipliers. The prototype fabricated in 0.35-/spl mu/m CMOS demonstrates that the 54 b/spl times/54 b multiplier consumes only 53.4 mW at 3.3 V for 74-MHz operation.

Constant-time addition and simultaneous format conversion based on redundant binary representations

It is well-known that constant-time addition, in which the execution delay is independent of operand lengths, is feasible only if the output is expressed in a redundant representation. There are many ways of introducing redundancy and the specifics of the redundant format employed can have a major impact on the performance of constant-time addition and digit set conversion. This paper presents a comprehensive analysis of constant-time addition and simultaneous format conversion. We consider full as well as partially redundant representations, where not all digit positions are redundant. The number of redundant digits and their positions can be arbitrary, yielding many possible redundant representations. Format conversion refers to changing the number and/or position of redundant digits in a representation. It is shown that such a format conversion is feasible during (ie, simultaneous with) constant time addition, even if all three operands (the two inputs and single output) are represented in distinct redundant formats. We exploit equal-weight grouping (EWG), wherein bits having the same weight are grouped together to achieve the constant-time addition and possible simultaneous format conversion. The analysis and data show that EWG leads to efficient implementations. We compare VLSI implementations of various constant-time addition cells and demonstrate that the conventional 4:2 compressor is the most efficient way to execute constant time-addition. We show interesting connections to prior results and indicate possible directions for further extensions.