An efficient redundant binary adder with revised computational rules

Abstract

Redundant binary representation (RBR) offers a carry-free addition of two redundant binary (RB) numbers. The computational rules of the conventional RB adder (CRBA) generate intermediate sum and carry vectors in RBR, leads to area overhead and pre-hardware elements for reverse conversion (RC). We have considered that the intermixing of inverted encoding of negabits (IEN) representation and conventional binary bits or posibits can be realized using standard hardware blocks. This paper provides a new computational rule for RB adder generating the intermediate sum and intermediate carry in posibit and IEN representations replacing the redundant digits. Thus, the proposed RB adder provides a single stage RB adder omitting the requirement of intermediate RB digits. For circuit synthesis of the proposed designs, we have considered Encounter® RTL Compiler and Xilinx Synthesis Technology in ASIC and FPGA platforms respectively. The comparative study of proposed NRBA offers improved design parameters as compared to CRBA.