A modified redundant binary adder for efficient VLSI architecture

Abstract

Signed digit representation is vital for implementation of fast arithmetic algorithm and efficient hardware realization. Redundant binary (RB) number representation is the most widely used technique for representation of signed digit number. Again RB representation has ability to provide carry propagation free addition. In this paper we have presented an efficient modified redundant binary (MRB) adder by revising computational rules for the first step of carry propagation free addition. In the proposed MRB computational rule, the intermediate sum and intermediate carry are obtained in terms of conventional (Posibits) and inverted encoding of Negabits (IEN) representation replacing the redundant digits. The proposed MRB adder is synthesized and simulated using Xilinx-ISE 14.4 software and implemented on vertex-4 FPGA device. The propagation delay and device utilization are obtained from synthesis report and are compared with conventional redundant binary adder. The synthesis report for this proposed adder shows it has significant improvement in terms of combinational delay and area. Therefore it may be useful for designing high performances VLSI architectures.