Redundant Architecture Research Articles

Design of Optical Fiber Communication Networks for Feeder Automation

This paper focuses on design aspect of communication network for feeder automation applications. First, the business functional requirements of feeder automation and the supporting communication technologies are reviewed. Then, based on typical loop sectionalizing feeder connecting scheme, the communication infrastructure using Ethernet Passive Optical Networks (EPONs) is presented, and the redundant PON architecture is adopted.

Estimating sustainability impact of high dependable data centers: a comparative study between Brazilian and US energy mixes

The advent of services such as cloud computing, social networks and e-commerce has led to an increased demand for computer resources from data centers. Prominent issues for data center designers are sustainability, cost, and dependability, which are each significantly affected by the redundant architectures required to support these services. Within this context, models are important tools for designers when attempting to quantify these issues before implementing the final architecture. This paper proposes a set of models for the integrated quantification of the sustainability impact, cost, and dependability of data center power and cooling infrastructures. This is achieved with the support of an environment called ASTRO. The approach taken to perform the system dependability evaluation employs a hybrid modeling strategy which recognizes the advantages of both stochastic Petri nets and reliability block diagrams. Additionally, an energy flow model is proposed to estimate the environmental impact and cost of data center architectures whilst respecting the energy constraints of each device. This work also presents a case study which analyzes the environmental impact and dependability metrics as well as the operational energy cost of real-world data center power and cooling architectures within the context of the energy mixes of the US and Brazil.

On Effective Through-Silicon Via Repair for 3-D-Stacked ICs

3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3-D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleanness of silicon dies, rendering prior TSV redundancy solutions less effective. Furthermore, existing techniques consume a lot of redundant TSVs that are still costly in the current TSV process. This inefficient TSV redundancy can limit the amount of TSVs that is allowed to use and may even become the obstacle to commercial production. To resolve this problem, we present a novel TSV repair framework, including a hardware redundancy architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, the corresponding repair algorithm and the redundancy architecture construction. By doing so, the manufacturing yield for 3-D-stacked ICs can be dramatically improved, as demonstrated in our experimental results.

Inversion-Based Control of a Highly Redundant Military HEV

This paper deals with the control design of a military hybrid electric vehicle (HEV). The studied vehicle presents a highly redundant architecture to ensure high system reliability. As a consequence, the control scheme is complex to design. Energetic macroscopic representation (EMR) is used to describe the interaction between all subsystems of the powertrain. A control structure is deduced by an inversion of the EMR of the vehicle powertrain. Simulation results demonstrate the ability of this inversion-based control to achieve military missions.

New Redundant Architectures in Machining: Serial and Parallel Robots

New machine architectures were born during these last years pushed by industrial exigencies in terms of productivity. In this paper, we propose to study the performances that two new machining architecture including hybrid robot with a parallelogram closed loop and a parallel structure can offer. These two robots are combined with a 2 axis turntable in a 8 DoFs robotic cell. Three redundant parameters are used to optimize the path planning. The criteria used to optimize the behavior of each robotic cell and to assess their behavior are presented in this paper along with a comparative study of the kinematic performances and stiffness performances of the two architectures.

Fuzzy Multi-Objective Software Reliability Redundancy Allocation Based on MEDA-BFA Algorithm

Software reliability allocation problem is a major problem in engineering design practices. A fuzzy multi-objective software reliability allocation model is established by analyzing the software redundancy architecture and considering some fuzzy factors to reliability. Then, the MEDA-BFA algorithm is proposed based on estimation of distribution to solve software reliability redundancy allocation problem. Finally, experimental results show that the proposed intelligence algorithm can solve multi-objective software reliability allocation effectively and correctly, can help decision makers decide between software reliability and cost.

DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and Its Case Study of Radiation Stress Test

A microprocessor with an architectural redundancy to achieve high dependability is designed and manufactured to explore the effectiveness of tolerating soft errors without circuit hardening. The processor architecture is based on a modularized pipeline which contains several functionalities to facilitate a real-time error detection and a fast roll-back recovery. As a further extension for a possible increase of hard errors in the future technology, an energy-effective coverage of hard errors by dynamically adapting the redundancy between a dual and a triple module is also included in the processor. A radiation stress test result indicates that the designed redundant but unhardened processor can successfully achieve the same dependability as a hardened processor. Our synthesis and layout results show that radiation hardened circuits increase processor hardware area by 71% and power by 28%, respectively. It is thus possible to use the architectural redundancy instead of circuit hardening to achieve a cost-effective reliability, as suggested by these factors.

Submitting of Architectural Redundancy Concept through the Study on Changes in Per Capita Living Space Demands of Urban Residences

At present, China is the country with the maximum quantity of annual new construction in the world, but the average life of the buildings is very short. Through the analysis of the urban per capita living space of macro data variations and individual environmental psychology, it is raised that design lacks of “redundancy" is one of the important reasons.”Redundancy" is to consider the future needs in design , "redundancy" concept is introduced in the field of architecture, for solving that our country’s building lives are generally in a short situation. It is also an important way to realize the sustainable development.

Reliability Models of GSM-R Redundant Network on High-Speed Railway

As a dedicated digital mobile communication system designed for railway application, GSM-R must provide reliable bidirectional channel for transmitting security data between trackside equipments and on-train computer on high-speed railways. To ensure the safety of running trains, redundant network architecture is commonly used to guarantee the reliability of GSM-R. Because of the rigid demands of railway security, it is important to build reliability mathematical models, predict the network reliability and select a suitable one. Two common GSM-R wireless architectures, co-sited double layers network and intercross single layer network, are modeled and contrasted in this paper. By calculating the reliabilities of each reliable model, it is clear that more redundant the architecture is, more reliable the system will be, the whole system will bear a less failure time per year as the benefit. Meanwhile, as the redundancy of GSM-R system raises, its equipment and maintenance will cost much, but the reliability raise gently. From the standpoint of transmission system interruption and network equipment failure, the reliability of co-sited double layer network architecture is higher than the intercross single layer one, while the viability and cost of the intercross redundant network is better than co-sited one in natural disasters such as flood and lightning. Taking fully into account reliability, viability and cost, we suggest that intercross redundant network should be chosen on high-speed railway.

Adaptive Fault-Tolerant Architecture for Unreliable Technologies With Heterogeneous Variability

This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure that is able to cope with nonhomogeneous variability and time-varying effects like degradation and external aggressions, which are expected to be key limiting factors in future technologies. First, we consider static heterogeneity of the input variability levels and derive a methodology to determine the weight values that maximize the reliability of the averaging system. The implementation of these optimal weights in the AVG gives place to the unbalanced AVG structure (U-AVG). Second, we take into consideration that circuits are exposed to time-dependent aggression factors, which can induce significant changes on the levels of variability, and introduce the adaptive AVG structure (AD-AVG). It embeds a learning mechanism based on a variability monitor that allows for the on-line input weight adaptation such that the actual weight configuration properly reflects the aging status. To evaluate the potential implications of our proposal, we compare the conventional AVG architecture with the unbalanced (U-AVG) and the adaptive (AD-AVG) approaches in terms of reliability and redundancy overhead by means of Monte Carlo simulations. Our results indicate that when AVG and U-AVG are exposed to the same static heterogeneous variability, U-AVG requires 4 less redundancy for the same reliability target. Subsequently, we include temporal variation of input drifts in the simulations to reproduce the effects of aging and external aggressions and compare the AVG structures. Our experiments suggest that AD-AVG always provides the maximum reliability and the highest tolerance against degradation. We also analyze the impact of nonideal variability monitor on the effectiveness of the AD-AVG behavior. Finally, specific reconfigurable hardware based on resistive switching crossbar structures is proposed for the implementation of AD-AVG.

Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs

In this paper, efficient built-in self-repair (BISR) techniques for multiple repairable memory cores with different sizes and divided redundancy mechanisms are proposed. Embedded memory cores are first partitioned into memory groups. For each memory group, a redundant memory module is added and divided into row blocks and column blocks. Moreover, the memory cores within a memory group are partitioned into divided arrays (consisting of row/column blocks) of the same size. The redundant memory can be shared among all memory cores within the same memory group. Therefore, unlike the traditional redundancy architectures, a row (column) block is used as the basic replacement element. Based on the proposed redundancy architecture, a heuristic heterogeneous extended spare pivoting redundancy analysis algorithm suitable for built-in implementation is also proposed. Experimental results show that the repair rate and manufacturing yield can be improved significantly due to the efficient usage of redundancy. Moreover, the area overhead of the BISR circuitry for an example memory group consisting of four memory instances of size 9.25 Mbits is only 1.12%.

Exploring redundant arithmetics in computer-aided design of arithmetic datapaths

The rapid pace of technological evolution places a substantial amount of pressure on minimizing the time-to-market for integrated circuit designers. Such pressure on the design cycle combined with strict performance constraints makes the use of computer-aided design tools mandatory. In this context, CAD tools that improve performance in terms of delay, area or power consumption are of interest.In this paper, we present a design environment that is dedicated to arithmetic datapath design support. This environment consists of the following elements: (1) Stratus: a language that is dedicated to the parameterized generation of VLSI modules and that allows several levels of abstraction; (2) ArithLib: a library of parameterized arithmetic IP-block generators; and (3) several optimization algorithms that choose the best architecture for each arithmetic operator of a datapath, given an optimization goal. These algorithms consider binary arithmetic as well as redundant arithmetic, given the good intrinsic performance of redundant architectures. In addition, experimental results are presented.

RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path

Recently, the DVS (Dynamic Voltage Scaling) method has been aggressively applied to processors with Razor Flip-Flops. With Razor FF detecting setup errors, the supply voltage in these processors is down-scaled to a near critical setup timing level for a maximum power consumption reduction. However, the conventional Razor and DVS combinations cannot tolerate well error rate variations caused by IR-drops and environment changes. At the near critical setup timing point, even a small error rate change will result in sharp performance degradation. In this paper, we propose RazorProtector, a DVS application method based on a redundant data-path which uses a multi-cycle redundant calculation to shorten the recovery penalty after a setup error occurrence. A dynamic redundancy-adapting scheme is also given to use effectively the designed redundant data-path based on a study of the program, device and error rate characteristics. Our results show that RazorProtector with the adaptive redundancy architecture can, compared to the traditional DVS method with Razor FF, under a large setup rate caused by a 10% unwanted voltage drop, reduce EDP up to 78% at 100µs/V, 88% at 200µs/V voltage scaling slope.

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration

This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area in a 0.13-μm CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.

Progressive module redundancy for fault-tolerant designs in nanoelectronics

Redundancy techniques are widely used to increase the reliability of the circuits. This paper proposes an efficient method to select the best subset among possible redundant architectures. It builds upon the progressive module redundancy technique and the block grading concept. Furthermore, this method is not constrained on TMR but extends to 5MR. Experiment results demonstrate its advantages in efficiency, reliability and cost. The proposed method points out a new direction of economical redundant fault-tolerant designs for nanoelectronics.

Task-Specific Multiple-Arm Minimally Invasive Surgical Device Design Using Cooperative Kinematic Isotropy Indices

The transition from multiple-port to single-port robotic systems in minimally invasive surgery (MIS) procedures has made flexible, dexterous manipulation an essential capability. The requirement that single-port MIS devices span an enclosed surgical workspace through only one access point while avoiding collateral damage to surrounding tissues necessitates the employment of mechanically sophisticated, kinematically redundant device architectures. These redundant architectures, while capable of achieving clinically-acceptable performance levels on complicated MIS procedures, are difficult to design and can easily result in economically prohibitive or technically impractical solutions. The problem of balancing clinical functionality and design economy in single-port MIS devices becomes even more challenging when the dexterous use

Heavy-Ions induced SEE effects measurements for the STRURED ASIC

With the aim of developing a radiation-tolerant circuit, a digital test microelectronic device has been designed and fabricated by using a standard-cell library of a 130-nm CMOS technology, including three different architectures to correct circuit malfunctions induced by the occurrence of Single-Event Effects (SEEʼs). SEEʼs are one of the main reasons of failures affecting electronic circuits operating in harsh radiation environments, such as in experiments performed at High Energy Physics (HEP) colliders or in apparatus to be operated in Space. On the same digital circuit specifically designed, three redundant architectures added to a basic scheme have been implemented in order to evaluate their effectiveness to prevent SEE. This may give an indication on their usage in future digital circuits specifically designed for the above mentioned applications. We present the results of SEE cross section measurements performed on a test digital device exposed to a high energy heavy ion beam at the SIRAD irradiation facility of the INFN National Laboratories of Legnaro (Padova Italy).

Software safety analysis application of safety-related I&C systems in installation phase

This work performed a software safety analysis (SSA) in the installation phase of the Lungmen nuclear power plant (LMNPP) in Taiwan, under the cooperation of INER and TPC. The US Nuclear Regulatory Commission (USNRC) requests licensee to perform software safety analysis (SSA) and software verification and validation (SV&V) in each phase of software development life cycle with Branch Technical Position (BTP) 14. In this work, 37 safety grade digital instrumentation and control (I&C) systems were analyzed by Failure Mode and Effects Analysis (FMEA), which is suggested by IEEE Standard 7-4.3.2 (2003). During the installation phase, skew tests for safety grade network and point to point tests were performed. The FMEA showed all the single failure modes can be resolved by the redundant architecture. The common mode failures can be resolved by operator manual actions via the diverse displays.

Reliability Analysis for Train Control System by Hardware Redundancy Architecture in Fault Tolerance System

Train control system is a vital system due to controlling the speed and interlocking of train in railway. The train control system is designed by double module or triple module system as a vital system. Hardware redundancy means to use additional hardware to defect and tolerant faults. There are three forms of hardware redundancy: passive, active and hybrid. Passive redundancy architecture achieves fault tolerance by masking the faults that occur without requiring any action on the part of the system or an operator. Active redundancy architecture requires a fault to be detected before it can be tolerated. After the detection of the fault, the actions of location, containment and recovery are performed to remove the faulty component from the system. Hybrid redundancy architecture combines passive and active approaches. Fault masking is used to prevent generation of erroneous results. Fault detection, location and recovery are used to replace the faulty component with a spare component. In this paper, the architecture and reliability model are presented through the passive, active, hybrid redundancy architecture. Also, the reliability in the train control system is analyzed through changing time using Matlab program.

Realizing Fault-Tolerant Asynchronous Sequential Machines Using Corrective Control

A control scheme is presented for realizing state fault-tolerance of asynchronous sequential machines. An unobservable disturbance input can infiltrate into asynchronous machines and provoke unauthorized state transitions. The objective is to propose automatic state feedback controllers that detect penetration of the disturbance input and counteract state faults so as to return the controlled machine to its original state. A necessary and sufficient condition for the existence of such a controller is presented in a theoretical framework and an architecture of asynchronous triple modular redundancy is addressed as a case study.