Redundancy Scheme Research Articles

A low-power instruction replay mechanism for design of resilient microprocessors

There is a growing concern about the increasing rate of defects in computing substrates. Traditional redundancy solutions prove to be too expensive for commodity microprocessor systems. Modern microprocessors feature multiple execution units to take advantage of instruction level parallelism. However, most workloads do not exhibit the level of instruction level parallelism that a typical microprocessor is resourced for. This offers an opportunity to reexecute instructions using idle execution units. But, relying solely on idle resources will not provide full instruction coverage and there is a need to explore other alternatives. To that end, we propose and evaluate two instruction replay schemes within the same core for online testing of the execution units. One scheme (RER) reexecutes only the retired instructions, while the other (REI) reexecutes all the issued instructions. The complete proposed solution requires a comparator and minor modifications to control logic, resulting in negligible hardware overhead. Both soft and hard error detection are considered and the performance and energy impact of both schemes are evaluated and compared against previously proposed redundant execution schemes. Results show that even though the proposed schemes result in a small performance penalty when compared to previous work, the energy overhead is significantly reduced.

A novel redundant haar lifting wavelet analysis based fault detection and location technique for telephone transmission lines

The redundant lifting scheme is a perfect tool for wavelet decomposition and reconstruction conducted in the time domain without decimation procedure. In this paper based on the redundant haar lifting wavelet analysis and time domain reflectometry (RHLW-TDR) a novel fault detection scheme is introduced to detect the fault of the telephone transmission lines. The fault time tags are extracted directly from the wavelet detail coefficients. Furthermore, the proposed algorithm is improved to adaptive morphological redundant haar lifting wavelet analysis based time domain reflectometry (AMRHLW-TDR). Comparing to the conventional wavelet based TDR technique, the simulation test and practical experiment results verified the accuracy and convenience enhancement of the proposed methodology and its improved version.

Design, Analysis and Implementation of Improved Adaptive Fault Tolerant Model for Cruise Control Multiprocessor System

or mission critical applications have to recover from an error within an acceptable time window or it may potentially lead to disastrous effects or higher costs. The usual industrial practice is to employ fault tolerance using hardware redundancy where costs are highly exorbitant depending on the mission. In this paper, we present a framework for adaptive fault tolerance on the commonly used hardware redundancy. This proposed model gives enhanced resource management and improved system performance under normal runtime and provides minimal safe functionality under error conditions. A new scheduling method, a combination of dynamic planning and dynamic best effort approach has been designed for joint scheduling of periodic and aperiodic tasks which also include online reconfiguration for error management. This fault recovery technique allows all critical tasks to meet their deadlines and the system continues functioning with minimal safe functionality upon errors. This model has been analyzed and evaluated on a practical case study of a Cruise Control System vis- a-vis a traditional redundancy scheme with simulation and validated with appropriate performance metrics. The results demonstrate the high performance throughput and process speedup (Execution time of process) that can be gained by applying this model to an m-processor redundancy model and the advantages can be accrued specially in the field of avionics in terms of fuel/weight ratio.

The Redundant Design and Reliability Analysis of Magnetic Bearings Used for Aeroengine

The redundant design principle of weak coupling magnetic bearing system for aeroengine is put forward. A redundant design scheme of weak coupling magnetic bearing system is provided including radial and axial magnetic bearings and their control system. The performance of the weak coupling redundant magnetic bearing is analyzed with the finite element method and then compared with the strong coupling redundant magnetic bearing. The weak coupling redundant magnetic bearing has some advantages in both redundancy and load bearing capacity under the circumstance of either no failure or partial failure in the coils. In view of the increase in the number of electronic components in the control system, both reliability and redundancy are evaluated comprehensively. A compromise solution of 12-pole structure for the weak coupling redundant magnetic bearing is recommended.

Robust node-disjoint multipath routing for wireless sensor networks

In wireless sensor networks WSNs, disjoint multipath routing has gotten immense research interest due to its capability of providing high reliability and load balancing. In this paper, we present a robust node-disjoint multipath routing RNMR protocol for WSNs. The protocol first constructs a multi-routing tree which has a number of node-joint but link-disjoint subtrees, and then finds multiple paths along these subtrees. Furthermore, by taking advantage of the structural characteristics inherent in the multi-routing tree, we present a customised redundancy scheme to improve the reliability of data transmission. The scheme provides individualised data redundancy for each sensor node. The protocol does not need to employ any control beacons in the data routing phase. Theoretical analysis and simulation results show that our protocol achieves higher reliability, reduces end-to-end delay and improves energy efficiency compared with existing approaches.

Fault Tolerant Quadded Logic Cell Structure with Built-in Adaptive Time Redundancy

This paper describes research carried out using a quadded logic cell (QLC) structure with the purpose of creating a fault tolerant strategy for stuck-at faults. In order to create the tolerant built-in behaviour, the basic logic elements must have resilience against transistor level stuck-at failures. To achieve this, we add fine-grained redundancy to the transistor structure of the individual logic gates. In our research NAND gates which are been used throughout the QLC design. Simulation data shows that the chosen enhanced NAND gate structure can cope with single random stuck-at fault and if not indicates it through a distinct current indication. The QLC design contains four individual logic units which can be configured to perform four different types of two input logic functions. The QLC contains an interconnection structure that links three logic units to form a logic structure with four inputs and one output. This fixed internal structure revolves clockwise in four steps in a “round-robin” time redundancy scheme to create a set number of results. Through a majority voting a combined overall output result gets generated. Individual comparison of each clock cycle result against the voted result reveals the cycle and logic unit combination in which the faulty result has been generated. In this case alteration of the individual logic unit configuration has been used to generate another set of results for pattern mapping to identify the single logic unit within the QLC. After identification a self-initiated logic unit replacement with a spare unit happens. An additional detection method based on power rail grading of the individual logic units is devised to enable built-in classification of the stuck-at fault occurring within the unit and subsequently to trigger self-repair. These features are intended to be self-coordinated without requiring outside influence, making this resulting design capable of autonomous self-healing under specific failure conditions.

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Nano-scale devices are continuously shrinking, operating at lower voltages and higher frequencies. This makes them more susceptible to environmental perturbations and distinguished by their high dynamic fault rates. Redundancy techniques are widely used to increase the reliability of combinational logic circuits. In this work, soft error reliability is improved by using such techniques, and based on probability of occurrence for combinations at the outputs of circuits. A generalized modular redundancy scheme to enhance the reliability of combinational circuits is proposed. Additionally, several aspects regarding the application of this scheme are explored. This comprises types of redundant modules, complexity of voters and single versus multiple outputs protection. Also, a methodology for applying the generalized modular redundancy scheme is developed. Reliability analysis for various benchmarks from the LGSynth91 suite shows that the proposed methodology can achieve reliability figures higher than that of triple modular redundancy. In general, significant overhead savings are accomplished in addition to that superior reliability.

Design and Kinematical Performance Analysis of a 3-RUS/RRR Redundantly Actuated Parallel Mechanism for Ankle Rehabilitation

In this paper, we present the design of a novel 3-RUS/RRR redundantly actuated parallel mechanism for ankle rehabilitation based on the principle from the conceptual design. The proposed mechanism can actualize the rotational movements of the ankle in three directions while at the same time the mechanism center of rotations can match the ankle axes of rotations compared with other multi-degree-of-freedom devices, owing to the structural characteristics of the special constraint limb and platform. A new actuator redundancy scheme is used, which not only still maintains all inherent advantages from actuator redundancy but also possesses the kinematic partially decouple feature that improves the flexibility of the robotic system. Kinematic performances, such as dexterity, singularity and stiffness, are analyzed based on the computed Jacobian. Then simulation is performed. All the results show that the redundant robot has no singularity, better dexterity and stiffness within the prescribed workspace in comparison with the corresponding 3-RUS/RRR nonredundant robot, and is suitable for rehabilitation exercise.

High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design

In a modern high density VLSI design, with higher operating frequency and technology scaling, small critical charge in circuit nodes significantly increases susceptibility to radiation induced transient faults. In this paper, we propose a high efficiency hardened latch using the undesired delay of Schmitt trigger circuit and a special feedback loop to a comparator to build a low overhead time redundancy scheme. The proposed structure masks internal node transient faults also improves the recovery of the output node by transferring the faulty output in two different paths to the comparison circuit's inputs. Experimental results, simulated in 45 nm CMOS technology, show an acceptable increase in the critical charge compared with the previous hardened latches, with a fair increase in power, delay and area. Monte Carlo simulations have also confirmed the proposed latch resistance to the process, voltage and temperature variations.

Industrial legislation in Australia in 2012

The year 2012 produced a high volume of developments in the industrial relations law sphere. The Review of the operation of the Fair Work legislation dominated the federal agenda and, accordingly, is the primary focus of this article. We detail key recommendations and outcomes of the Review, including associated amendments. Next, we consider other federal changes, which were expansive in focus. Federal reforms included: a new legislated employee entitlements scheme to replace the administrative General Employee Entitlements and Redundancy Scheme; new regulation of the road transport industry; an overhaul of workplace gender equality legislation; revised governance obligations for registered organisations; and the introduction of the ‘dad and partner pay’ scheme as part of the Commonwealth's parental leave package. Turning to the states and territories, we summarise public sector workplace law changes in both New South Wales and Queensland and address other notable developments across jurisdictions.

Radiation-hard/high-speed parallel optical links

We have designed an ASIC for use in a parallel optical engine for a new layer of the ATLAS pixel detector in the initial phase of the LHC luminosity upgrade. The ASIC is a 12-channel Vertical Cavity Surface Emitting Laser (VCSEL) array driver capable of operating up to 5Gb/s per channel. The ASIC is designed using a 130nm CMOS process to enhance the radiation-hardness. A scheme for redundancy has also been implemented to allow bypassing of a broken VCSEL. The ASIC also contains a power-on reset circuit that sets the ASIC to a default configuration with no signal steering. In addition, the bias and modulation currents of the individual channels are programmable. We have tested the ASIC and the performance up to 5Gb/s is satisfactory. Furthermore, we are able to program the bias and modulation currents and to bypass a broken VCSEL channel. We are currently upgrading our design to allow operation at 10Gb/s per channel yielding an aggregated bandwidth of 120Gb/s. Preliminary results of the design will be presented.

Design of exact regenerating hierarchical code for distributed storage system

Erasure code is widely used as the redundancy scheme in distributed storage system. When a storage node fails, the repair process often requires to transfer a large amount of data. Regenerating code and hierarchical code are two classes of codes proposed to reduce the repair bandwidth cost. Regenerating codes reduce the amount of data transferred by each helping node, while hierarchical codes reduce the number of nodes participating in the repair process. In this paper, we propose a “sub-code nesting framework” to combine them together. The resulting regenerating hierarchical code has low repair degree as hierarchical code and lower repair cost than hierarchical code. Our code can achieve exact regeneration of the failed node, and has the additional property of low updating complexity.

A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

A Novel Lossless Robust Watermarking Method for Copyright Protection of Biomedical Image

Nanoscience and Nanotechnology promotes the development of biomedical imaging devices, more and more valuable biomedical images are transmitted through the open network, and their copyright suffers a major challenge. This paper proposes a new lossless robust watermarking method to realize biomedical image's copyright protection. For high-resolution biomedical images, the redundant theory and histogram shifting method based on image block's difference are utilized to repeatedly embed copyright watermark into different color channels. In the extracting procedure, each layer's watermark information can be extracted from watermarked image respectively, and the final watermark is judged by the voting theory. The redundant scheme and voting theory guarantees the watermark can resist against random noise's attack well. Besides, in order to reduce the watermark overhead in embedding procedure, the histogram narrowing down technique is used to tackle with those image blocks would overflows and underflows. Experimental results showed that the proposed method outperformed the existing semi-fragile reversible watermarking scheme and provided a great robustness against moderate JPEG compression and salt-pepper and Gaussian noise.

철도차량 통신 네트워크(TCN)에서의 WTB 이중화에 대한 프로토콜 분석 플랫폼

TCN(train communication network) standard was approved in 1999 by the IEC (IEC 61375-1) and IEEE (IEEE 1473-T) organizations to warrant a reliable train and equipment interoperability. TCN defines the set of communication vehicle buses and train buses. The MVB(multifunction vehicle bus) defines the data communication interface of equipment located in a vehicle and the WTB(wire train bus) defines the data communication interface between vehicles. The WTB and each MVB will be connected over a node acting as gateway. Also, to support applications demanding a high reliability, the standard defines a redundancy scheme in which the bus may be double-line and redundant-node implemented. In this paper we have presented protocol analysis platform for the WTB redundancy which is part of TCN system, to verify communication state of high-speed trains. As a confirmation of its validity, the technology described in this paper has been successfully applied to state monitoring and protocol verification of redundancy WTB based on TCN.

Customized Multiwavelets for Planetary Gearbox Fault Detection Based on Vibration Sensor Signals

Planetary gearboxes exhibit complicated dynamic responses which are more difficult to detect in vibration signals than fixed-axis gear trains because of the special gear transmission structures. Diverse advanced methods have been developed for this challenging task to reduce or avoid unscheduled breakdown and catastrophic accidents. It is feasible to make fault features distinct by using multiwavelet denoising which depends on the feature separation and the threshold denoising. However, standard and fixed multiwavelets are not suitable for accurate fault feature detections because they are usually independent of the measured signals. To overcome this drawback, a method to construct customized multiwavelets based on the redundant symmetric lifting scheme is proposed in this paper. A novel indicator which combines kurtosis and entropy is applied to select the optimal multiwavelets, because kurtosis is sensitive to sharp impulses and entropy is effective for periodic impulses. The improved neighboring coefficients method is introduced into multiwavelet denoising. The vibration signals of a planetary gearbox from a satellite communication antenna on a measurement ship are captured under various motor speeds. The results show the proposed method could accurately detect the incipient pitting faults on two neighboring teeth in the planetary gearbox.

Analyzing job completion reliability and job energy consumption for a general MapReduce infrastructure

Recently, MapReduce has been a popular distributed programming framework, which divides a job into map tasks and reduce tasks and executes these tasks in parallel over a large-scale MapReduce cluster to speed up job execution. Generally, the cluster is a master-slave infrastructure. To prevent jobs from being interrupted due to node failure, current MapReduce implementations, such as Hadoop, adopt a task-reexecution policy on the slave side, i.e., when a slave node due to failure cannot complete a task, this task will be reassigned to another available slave for reexecution. However, on the master side by default, no redundancy scheme is provided. Since this type of infrastructure has been worldwide adopted, we call it the general MapReduce infrastructure GMI. To achieve a more reliable and energy-efficient working environment, understanding the impact of GMI on its job completion reliability JCR and job energy consumption JEC is required. In this paper, we base on a Poisson distribution to analyze GMI's JCR from a single-job perspective. After that, we accordingly derive the corresponding JEC. Through the analytical results, MapReduce managers can comprehend how GMI behaves and how their MapReduce can be improved so as to achieve a more reliable and energy-efficient MapReduce environment.

DC-50 GHz RF-MEMS SPDT switch for high-reliability applications

A large band SPDT (single-pole double-throw) switch based on a very advanced RF-MEMS switch technology for redundancy schemes are presented. This device allowed to reach state-of-the-art working bandwidth (DC-50 GHz) and RF performances (IL (Insection loss) 25 dB, and RL > 20 dB). The 200 mm MEMS technology process has demonstrated a very good stability with very low dispersion (deviations < 0.05 dB for the IL and < 0.6 dB for the isolation over the entire wafer and frequency range). An accurate electrical equivalent circuit, modeling the SPDT in the DC-65 GHz frequency band, has allowed to extract a contact resistance which is as low as 1.4 Ω. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:333–335, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27330

Radiation-hard/high-speed parallel optical engine

We have designed an ASIC for use in a parallel optical engine for a new layer of the ATLAS pixel detector in the initial phase of the LHC luminosity upgrade. The ASIC is a 12-channel VCSEL (Vertical Cavity Surface Emitting Laser) array driver capable of operating up to 5 Gb/s per channel. The ASIC is designed using a 130 nm CMOS process to enhance the radiation-hardness. A scheme for redundancy has also been implemented to allow bypassing of a broken VCSEL. The ASIC also contains a power-on reset circuit that sets the ASIC to a default configuration with no signal steering. In addition, the bias and modulation currents of the individual channels are programmable. We have received the ASIC and the performance up to 5 Gb/s is satisfactory. Furthermore, we are able to program the bias and modulation currents and to bypass a broken VCSEL channel. We are currently upgrading our design to allow operation at 10 Gb/s per channel yielding an aggregated bandwidth of 120 Gb/s. Some preliminary results of the design will be presented.

Cooperation Achieves Optimal Multicast Capacity-Delay Scaling in MANET

In this paper, we focus on capacity-delay tradeoffs for multicast traffic pattern. Under the assumption that n nodes move in a unit square according to an i.i.d. mobility model, with each serving as a source that sends identical packets to k destinations, we propose four schemes of which the achievable capacity λ and delay D are analyzed: (1) 2-hop noncooperative non-redundancy scheme, (2) 2-hop noncooperative redundancy scheme, (3) 2-hop cooperative non-redundancy scheme, (4) 2-hop cooperative redundancy scheme. Compared with non-cooperative scheme with capacity delay tradeoff λ = O( E[D]/nk log k) first developed in [5], cooperation among destination nodes achieves optimal capacity delay tradeoff λ = O(E[D]/n log k) in cell partitioned network. With intelligent cooperation, each destination acts equivalently as relay and helps other destinations get more opportunities of receiving packets with capacity sacrificed to a addition, our redundancy schemes also allow delay under Θ(√n) log k factor compared with unicast in [3] under the same delay. In achievable, which is the minimum delay under the schemes of [3],[5].