Time Redundancy Research Articles

Error prevention adaptive optimization model for power dispatch under time redundancy control

Error prevention adaptive optimization model for power dispatch under time redundancy control

Construction of a Computer Network Performance Prediction Optimization Model Based on Machine Learning Algorithms

Computer networks have been widely used in critical infrastructure for businesses, schools, governments, and individuals. The development of computer networks is an irreversible historical trend. This article studies computer network performance prediction optimization models through machine learning, which can improve the intelligence and efficiency of network management. Existing research has made some progress in machine learning based network security and performance optimization. However, good results have not been achieved in real-time performance prediction and optimization. This article uses Long Short Term Memory Network (LSTM) to establish an effective predictive optimization model. Firstly, the data is processed, such as missing values, duplicates, and device time redundancy. Then, features are selected to select the corresponding input features of the model. Finally, the model is optimized to obtain the optimized model. The performance of the LSTM model is compared with the random forest (RF) and support vector machine (SVM) models. Model performance indicators include mean absolute error (MAE), coefficient of determination, F1 score, and model computation time. The experimental results show that the LSTM model has higher accuracy than RF and SVM models in all evaluation metrics. Meanwhile, the LSTM model has significant advantages in computational time compared to the other two models. The LSTM based computer network performance prediction optimization model can be optimized in terms of prediction accuracy, generalization ability, and computational efficiency. It has the ability to effectively process time series data. The LSTM model used for network performance prediction has a minimum average absolute error of 8% and a maximum coefficient of determination of 0.95. It achieves higher F1 scores and faster calculation speed. The results reflect the potential and practicality of the LSTM model in optimizing computer network performance prediction.

Enhancing River Monitoring Embedded System using Time Redundancy Fault Tolerance to Resolve Transient Sensor Fault

Reading data from sensors in the context of the Internet of Things (IoT) is one of the main parameters of a high-reliability system. Data reading by sensors is prone to errors due to various variables that the problem cannot accommodate. One method to overcome this problem is the time redundancy algorithm, where the sensor takes data and its best value several times. In this study, the sensors used to calculate the water levels are ultrasonic sensors and resistance. At the river monitoring point, data is sent using the UDP (User Datagram Protocol) protocol that previous studies have used. This research has been done as a prototype with a maximum distance between sensor nodes of one meter. The results of sending data using UDP were successful, with an average delay of 3293 microseconds. And the ultrasonic sensor that has been tested based on transient fault against time redundancy has an accuracy of 94.5% based on a sampling delay of 1000ms.

A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors

This paper proposes a 13-bit two-step single-slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional method's time redundancy issue. The differential nonlinearity (DNL) and integral nonlinearity (INL) are simulated to be +0.8/-0.8 LSB and +2.1/-3.5 LSB, respectively, for the 55 nm 1P4M CMOS process. 512 ns is the conversion time of the 13-bit ADC. The power consumption is 47 μW, and the effective number of bits (ENOB) is 11.33 bits. In comparison to existing advanced ADCs, the method proposed in this paper can increase the ADC conversion rate by more than 60% while maintaining low power consumption and high precision, thereby providing theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.

Learning Spatiotemporal-Selected Representations in Videos for Action Recognition

Action recognition is a challenging task of modeling both spatial and temporal context. Numerous works focus on architectures modality and successfully make worthy progress on this task. While due to the redundancy in time and the limit of computation resources, several works focus on the efficiency study like frame sampling, some for untrimmed videos, and some for trimmed videos. With the intent of improving the effectiveness of action recognition, we propose a novel Computational Spatiotemporal Selector (CSS) to refine and reinforce the key frames with discriminative information in video. Specifically, CSS includes two modules: Temporal Adaptive Sampling (TAS) module and Spatial Frame Resolution (SFR) module. The former can refine the key frames in the temporal space for capturing the key motion information, while the latter can further zoom out some refined frames in the spatial space for eliminating the discrimination-irrelevant structural information. The proposed CSS is flexible to be embedded into most representative action recognition models. Experiments on two challenging action recognition benchmarks, i.e., ActivityNet1.3 and UCF101, show that the proposed CSS improves the performance over most existing models, not only on trimmed videos but also untrimmed videos.

Time-multiplexed vector light field display with intertwined views via metagrating matrix

Three-dimensional (3D) display is the future technology of display. The insufficient refreshable information provided by the screen is one of the major bottlenecks that hinders the development of light field 3D display. In this paper, a time-multiplexed vector light field display is proposed to increase the amount of information by exploiting the time redundancy. A view modulator with fully coverage of metagrating matrix is adopted to generate two groups of time-sequentially lit-up intertwined views. With a small deflection angle of incidence, the intertwined-view based time-multiplexing strategy is beneficial because of the less stray light and crosstalk, compared with the successively arranged views. Therefore, the system volume and complexity of directional backlight are reduced. In the experimental demonstration, a time-multiplexed vector light field 3D display is constructed with 18 views. The horizontal field of view reaches 51°. The potential applications include human-computer interaction, commercial exhibition, and medical hygiene.

Methodological provisions to the formation of district-distributed heating systems

The main methodological principles for the transformation of district heating systems into ones of a district-distributed type, optimally combining distributed (decentralized) and district (centralized) areas, are proposed, based on a comprehensive solution of problems of assessing the economic efficiency and reliability of heating to consumers. Wherein, the distributed sector is formed based on a prosumer that has its own generation, covering part of its own heat load and providing an additional functional and time redundancy for the system. As a result, сonclusions and directions for further research are formulated.

ПАРАМЕТРИЗАЦИЯ ТРЕБОВАНИЙ КОРРОЗИОННОЙ ЗАЩИЩЕННОСТИ СТАЛЬНЫХ КОНСТРУКЦИЙ

Basic provisions are presented of scientific and methodological substantiation of corrosion protectability of steel structures and installations. Priorities have been analyzed of improving existing codes, taking into account scientific achievements and international standards. Tasks have been formulated for increasing competitiveness and resource saving through the use of effective measures of corrosion protection. The study is aimed at parameterization of a mechanism of technical regulation of quality, reliability and safety, approval and application of materials and technologies, procedures, services in the field of corrosion protection at the request of a digital consumer. A process-oriented methodology is proposed aimed at a continuous improvement of development cycles and models of the rational choice of systems of corrosion protection of structures. With that, corrosion protection of structural steel is defined by the level of reliability and required parameters of technical and economic protection. The management structure is defined by the provisions of organization standard in accordance with ISO 12944, SP 28.1330.2017 with regard to corrosion protection of structural steel. The levels have been analyzed of reliability of structures and their protective coatings, with account for the procedures for assessing compliance of quality, monitoring and risk diagnostics based on the limit states method. Parameter compliance is affirmed based on five DMAIC principles related to determination, measurement, analysis, improvement and monitoring technical condition of structures. Examples are presented of statistical estimation of representative samples of corrosion impacts, characteristic values of corrosion resistance and durability of steel structures and their protective coatings. Proposed are methods for functional and time redundancy of corrosion protection assurance. Load testswere carried outof models of steel structures with corrosion damage. The obtained results reveal uncertainty of parameters of corrosion state and allow assessing structural steel survivability with account for acceptable risk. Suggestions for parametric design are recommended for digital transformation of the system of technical and economic regulators of corrosion protectability.

High‐gain ultra‐wideband quasi‐conical beam Fabry‐Perot antenna based on beam switching

To solve the contradiction between the high gain and wide coverage, the concept of the quasi-conical beam is proposed by using the high-gain pencil beam electrically switching along a cone to make full use of time redundancy. In a periphery-fed Fabry-Perot (FP)-type multi-beam antenna, the electrically switching is used to activate the different port corresponding to the different beam for the beam switching in the azimuthal plane, and the varying frequency is used for the continuous scanning in the elevation plane. Different from the lens or matrix multi-beam arrays, in this scheme, the FP cavity serves as both the beamforming network and the radiator to produce the multi-beam. Around eight planar antipodal Fermi-tapered slot antennas are placed around the FP cavity between the partially reflective surface and the metal ground plane as the primary feeds. The simulation and measurement results show that a relative impedance bandwidth of 53.3% with reflection coefficients below −10 dB from 11 to 19 GHz is obtained and the peak gain is 17.1 dBi at the central frequency of 15 GHz. The results also show that a high-gain beam scanning from 22° to 59° in the elevation plane is achieved and the peak gains are between 16 dBi and 20 dBi. In addition, when the electrically switching of the beam is along a cone, the proposed antenna may form quasi-conical beam. And in some applications, it may replace the conventional conical beam antenna with the advantages of wide coverage and high gain.

FT-EALU: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems

This paper presents a fault-tolerant ALU (“FT-EALU”) based on time redundancy and reward/punishment-based learning approaches for real-time embedded systems that face limitations in hardware and power consumption budgets. In this method, operations are diversified to three versions in order to correct permanent faults along with the transient ones. The diversities of versions considered in FT-EALU are provided by lightweight modifications to differentiate them and clear the effect of permanent faults. Selecting lightweight modifications such as shift and swap would avoid high timing overhead in computation while providing significant differences which are necessary for fault detection. Next, the replicated versions are executed serially in time, and their corresponding results are voted based on the derived learned weights. The proposed weighted voting module generates the final output based on the results and their weights. In the proposed weighted voting module, a reward/punishment strategy is employed to provide the weight of each version of execution indicating its effectiveness in the final output. To this aim, in the method defined for each version of execution, a weight is defined according to its correction capability confronting several faulty scenarios. Thus, this weight defines the reliability of the temporal results as well as their effect on the final result. The final result is generated bit by bit based on the weight of each version of execution and its computed result. Based on the proposed learning scheme, positive or negative weights are assigned to execution versions. These weights are derived in bit level based on the capability of execution versions in mitigating permanent faults in several fault injection scenarios. Thus, our proposed method is low cost and more efficient compared to related research which are mainly based on information and hardware redundancy due to employing time redundancy and static learning approach in correcting permanent faults. Several experiments are performed to reveal the efficiency of our proposed approach based on which FT-EALU is capable of correcting about \(84.93\%\) and \(69.71\%\) of permanent injected faults on single and double bits of input data.

A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors.

In emergent technologies, data integrity is critical for message-passing communications, where security measures and validations must be considered to prevent the entrance of invalid data, detect errors in transmissions, and prevent data loss. The SHA-256 algorithm is used to tackle these requirements. Current hardware architecture works present issues regarding real-time balance among processing, efficiency and cost, because some of them introduce significant critical paths. Besides, the SHA-256 algorithm itself considers no verification mechanisms for internal calculations and failure prevention. Hardware implementations can be affected by diverse problems, ranging from physical phenomena to interference or faults inherent to data spectra. Previous works have mainly addressed this problem through three kinds of redundancy: information, hardware, or time. To the best of our knowledge, pipelining has not been previously used to perform different hash calculations with a redundancy topic. Therefore, in this work, we present a novel hybrid architecture, implemented on a 3-stage pipeline structure, which is traditionally used to improve performance by simultaneously processing several blocks; instead, we propose using a pipeline technique for implementing hardware and time redundancies, analyzing hardware resources and performance to balance the critical path. We have improved performance at a certain clock speed, defining a data flow transformation in several sequential phases. Our architecture reported a throughput of 441.72 Mbps and 2255 LUTs, and presented an efficiency of 195.8 Kbps/LUT.

Optimal Task Abort and Maintenance Policies Considering Time Redundancy

For many practical systems that are required to perform critical tasks, it is commonly observed that tasks can be performed multiple times within a limited time to improve task success probability. Such property is referred to as time redundancy. This paper contributes by studying the optimal adaptive maintenance and the task abort strategies of continuously degraded systems considering two kinds of time redundancy to improve system safety and task reliability. The task abort decision is considered dynamically according to the degradation level and the number of task attempts. Task success probability and system survival probability under two kinds of time redundancy are evaluated using an event-based numerical algorithm. The optimal imperfect maintenance and task abort thresholds are investigated dynamically in each attempt to minimize the expected total cost of maintenance, task failure and system failure. The established model in this study is illustrated by numerical results.

A Low-cost Fault Tolerance Method for ARM and RISC-V Microprocessor-based Systems using Temporal Redundancy and Approximate Computing through Simplified Iterations

Approximate Computing techniques have been successfully used to reduce the overhead associated with redundancy in fault-tolerant system designs. This paper presents a fault tolerance method to reduce the execution time overhead of the well-known Time Redundancy technique by means of an improvement proposed for the Approximate Computing software-based technique known as loop perforation. Time Redundancy is a software-based fault tolerance technique that involves executing replicas of a task at different times. We propose to approximate the tasks to be executed using a new approximate computing technique based on loop perforation, i.e., simplified iterations. The novelty of this method is the combined use of the fault tolerance technique, temporal redundancy, jointly with the new proposed Approximate Computing technique, simplified iterations. The proposal is validated through simulation-based fault injection campaigns on several test programs for the ARM and RISC-V microprocessor architectures. Experimental results verified not only the applicability of the proposal in different architectures, but also its effectiveness, showing a good trade-off between reliability, error and overhead. Results showed that using the proposed method, a normalized mean work to failure (MWTF) up to 5.28× was obtained with approximation errors lower than those obtained using the traditional loop perforation technique.

Low-Cost Strategy to Detect Faults Affecting Scrubbers in SRAM-Based FPGAs

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to SEUs. For applications demanding high reliability this problem is often solved by integrating in the system a scrubber, a circuit that periodically scans the FPGA configuration memory and reconfigures it if an error is detected. Since the scrubber is usually implemented in the same FPGA device, it is also vulnerable to SEUs, thus the scrubber reliability is increased by adopting standard fault tolerance techniques. These solutions guarantee the scrubber reliability, but generally require a large area overhead.In this paper, we present a novel low-cost strategy capable to detect faults in the FPGA configuration memory implementing the scrubber. The proposed technique is based on time redundancy, forcing the scrubber output to produce an error indication for each word read from the FPGA memory, in order to detect the faults affecting the portion of FPGA memory implementing the scrubber. The implementation of our proposed strategy presents a negligible impact in terms of area overhead (4.17%) and a limited increase in power consumption (22.9%) over the original (unprotected) scrubber. As for the impact on system performance introduced by our strategy, it is of approximately the 38.2% over the unprotected scrubber, but it can be significantly lowered by reducing the frequency at which the scrubber is applied to test the FPGA.

Reliability Analysis of the Proactive Transmission of Replicated Frames Mechanism over Time-Sensitive Networking.

The Time-Sensitive Networking (TSN) Task Group has standardised different mechanisms to provide Ethernet with hard real-time guarantees and reliability in layer 2 of the network architecture. Specifically, TSN proposes using space redundancy to increase the reliability of Ethernet networks, but using space redundancy to tolerate temporary faults is not a cost-effective solution. For this reason, we propose to use time redundancy to tolerate temporary faults in the links of TSN-based networks. Specifically, in previous works we proposed the Proactive Transmission of Replicated Frames (PTRF) mechanism to tolerate temporary faults in the links. Now, in this work we present a series of models of TSN and PTRF developed using PRISM, a probabilistic model checker that can be used to evaluate the reliability of systems. After that, we carry out a parametric sensitivity analysis of the reliability achievable by TSN and PTRF and we show that we can increase the reliability of TSN-based networks using PTRF to tolerate temporary faults in the links of TSN networks. This is the first work that presents a quantitative analysis of the reliability of TSN networks.

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES.

Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.

Methodological Approach to Reducing and Evaluating Hardware and Time Redundancy of Means of Detecting and Correcting Packet Errors in Information Storage and Transmission Devices of Telecommunications Systems

Methodological Approach to Reducing and Evaluating Hardware and Time Redundancy of Means of Detecting and Correcting Packet Errors in Information Storage and Transmission Devices of Telecommunications Systems

A Comparative Analysis of the Online Scheduling System

Scheduling system is developed based on customers, individuals or organizational preferences in order to create an efficient and effective management of arrangement in prioritization, tasks, place and time. Some of scheduling systems will integrate a database for effective access of editing, viewing and recording amount of data. However, poor scheduling practices would cause undesirable time redundancy and inefficient process just to schedule a timetable for the lecturers and students. Poor scheduling also can cause a misunderstanding between lectures such as double-assignations of lectures, cancellations of presentations, clash in class schedule, prolonged postponement as well as inefficiency in terms of resources and time. A good scheduling system could generate optimal presentation of timetables and enable a direct interaction between lecturers and administration staff that will take into account all the constraints such as to check availability of time and place of events and real-time updates that will help data handling accuracy, cost effective and efficient time management. Therefore, this study will make a comparison and execute a standard process of scheduling framework for future practice in academic industry. This paper presents a practical method for making a comparison based on the studies on existing scheduling system.

A High-Reliability Redundancy Scheme for Design of Radiation-Tolerant Half-Duty Limited DC-DC Converters

Redundancy techniques are commonly used to design radiation- and fault-tolerant circuits for space applications, to ensure high reliability. However, higher reliability often comes at a cost of increased usage of hardware resources. Triple Modular Redundancy (TMR) ensures full single fault masking, with a >200% power and area overhead cost. TMR/Simplex ensures full single fault masking with a slightly more complicated circuitry, inefficient use of resource and a >200% power and area overhead cost, but with higher reliability than that of TMR. In this work, a high-reliability Spatial and Time Redundancy (TR) hybrid technique, which does not abandon a working module and is applicable for radiation hardening of half-duty limited DC-DC converters, is proposed and applied to the design of a radiation-tolerant digital controller for a Dual-Switch Forward Converter. The technique has the potential of double fault masking with a <2% increase in resource overhead cost compared to TMR. Moreover, for a Simplex module failure rate, λ, of 5%, the Reliability Improvement Factor (RIF) over the Simplex system is 20.8 and 500 for the proposed technique’s two- and three-module implementations, respectively, compared to a RIF over the Simplex system of only 7.25 for TMR and 14.3 for the regular TMR/Simplex scheme.

Trends of nutrients and metals in precipitation in northern Germany: the role of emissions and meteorology

We analyzed the precipitation chemistry for a maritime region in northern Germany (Schleswig–Holstein) from 1997 to 2017 in order to reveal temporal and spatial patterns and to evaluate the role of meteorological factors relative to emission reductions in Germany and Europe. Therefore, we applied several statistical methods such as time series decomposition, principal component, and redundancy analysis. We extracted two main groups: (i) a marine group (Cl, Na, Mg) that was related to natural processes like sea spray input and (ii) an anthropogenic group (Pb, Cd, As, Zn, and nitrogen species) with a terrestrial subgroup (Fe, Al, Mn), which were both related to emissions. These groups were valid for the spatial, seasonal, and annual trend data. Other elements, like Ca, K, total P, and sulfate, were influenced by natural and anthropogenic processes. The seasonal variation of ammonium deposition was caused primarily by ammonia emissions and ancillary by precipitation. Most heavy metals as well as sulfate, nitrate, and ammonium showed decreasing trends in concentrations and deposition fluxes. Only Hg did not show any trend. The decreasing depositions of sulfate and total nitrogen were correlated to emission reductions in Germany. The deposition of most heavy metals was influenced by emission reductions on European scale and meteorological factors such as wind speed and humidity. Hg did not show any correlation with the emission time series in Europe. Instead, it was correlated to the NAO index and wind, implying that global emissions and transport pathways determine the temporal development of Hg depositions. Overall, the study reveals that emission reductions positively influence regional depositions for most investigated substances. The regional spatial patterns of depositions were also influenced by local meteorological factors.