Reduce Power Dissipation Research Articles

Closed-Loop Deep Brain Stimulation With Reinforcement Learning and Neural Simulation.

Deep Brain Stimulation (DBS) is effective for movement disorders, particularly Parkinson's disease (PD). However, a closed-loop DBS system using reinforcement learning (RL) for automatic parameter tuning, offering enhanced energy efficiency and the effect of thalamus restoration, is yet to be developed for clinical and commercial applications. In this research, we instantiate a basal ganglia-thalamic (BGT) model and design it as an interactive environment suitable for RL models. Four finely tuned RL agents based on different frameworks, namely Soft Actor-Critic (SAC), Twin Delayed Deep Deterministic Policy Gradient (TD3), Proximal Policy Optimization (PPO), and Advantage Actor-Critic (A2C), are established for further comparison. Within the implemented RL architectures, the optimized TD3 demonstrates a significant 67% reduction in average power dissipation when compared to the open-loop system while preserving the normal response of the simulated BGT circuitry. As a result, our method mitigates thalamic error responses under pathological conditions and prevents overstimulation. In summary, this study introduces a novel approach to implementing an adaptive parameter-tuning closed-loop DBS system. Leveraging the advantages of TD3, our proposed approach holds significant promise for advancing the integration of RL applications into DBS systems, ultimately optimizing therapeutic effects in future clinical trials.

New, Fast, High-Performance Level Shifter for Buck DC-DC Converter in 180nm CMOS Technology

To reduce power dissipation, the dual supply voltage approach is required for analog circuits in the on-chip integrated circuits. In this paper, a novel circuit of the level shifter for Buck DC-DC Converter using cross-coupled configuration is presented. The proposed work of this paper uses this level shifter to converter voltage of 1.8V to 5V at 180 nm CMOS Technology in Cadence Virtuoso Tool. The propagation delay, energy/transition, and static power were 182.42pS, 0.01 fJ/Transition, and 6 fW, respectively. The final design area is only 60.142 μm2.

Reducing Power Dissipation in Memory Repair for High Fault Rates

Reducing Power Dissipation in Memory Repair for High Fault Rates

Comparative analysis of meta heuristics algorithm for differential amplifier design

The design of analog circuits is very essential for the development of system design based on electronics as the world is analog in nature. Furthermore, performance of emerging products depends on analog circuits for reduction of power dissipation and improvement of speed. Though in the system on chip (SoC) analog circuit consumes less, it is more complex to design it due to the analog circuit nature complexity. The job of the evolutionary algorithm (EA) in the process of optimization of an analog circuit based on complementary metal oxide semiconductor (CMOS) is to get the appropriate values that can be used for the design parameters of the given circuit in such a way such that all the targeted specification of the given circuit can be obtained. The chaotic serial particle swarm optimization (CSPSO) and cuckoo search (CS) algorithms are lower than to those found through the particle swarm optimization (PSO) and differential evolution (DE) algorithms. The CS algorithm obtained all the desired specifications with less power dissipation and the least total transistor area compared to those attained by the DE and PSO algorithms.

Pressure drop prediction in a pneumatic conveying system with different curvature radius pipes for conveying particles

To investigate the system pressure drop distribution when conveying particle using different curvature radius pipes for the pneumatic conveying system, this paper measured the particle velocity distribution, particle-particle collision characteristics, collision energy loss, minimum pressure drop gas velocity, system pressure drop distribution, and power dissipation for R/D = 3.75, R/D = 5, and R/D = 6.25 pipes. Subsequently, the artificial neural network technique is used to predict the pressure drop of the pneumatic conveying system. It is found that the pressure drop of the system is lower when using the pipe with R/D = 6.25 for conveying particles. Compared to the pipe with R/D = 3.75, the reduction in power dissipation is 3.18 and 5.27% for conveying pellets when using R/D = 5 and R/D = 6.25 pipes, respectively. In addition, the energy loss of the system can be effectively reduced when using the pipe with R/D = 6.25 for conveying particles, which is more beneficial for the particles move in the pipe. The pressure drop model built with artificial neural network can predict the pressure drop value of the system more accurately within ±1.5%.

A robust low-power fsm cordic lms filter design for exponential noise removal in pacemaker

ABSTRACT Heart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage, the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low-power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The least mean square (LMS) filter with Co-ordinate Rotation Digital Computer (CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly, the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies, leakage power has started to occupy 30–50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, integrated coarse-grained power and clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch-, AND- and OR-based clock gating with forced transistor stacking and sleep transistor whose width and length are doubled from the rest of the complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques are found to be 36.95% from the non-gated CORDIC LMS filter design.

Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations

This article analyzes the impact of ferroelectric hafnium zirconium oxide (HZO) thickness (tFE) and domain number (N) variations on the negative capacitance (NC) effect in metal/HZO/metal gate stack and its implications on Landau FET-based device-circuit co-design through simulations. As tFE decreases, the NC effect weakens, resulting in less S-shaped hysteresis loops for charge and polarization versus voltage characteristics. The study highlights the trade-off between energy dissipation and NC effect voltage window in ferroelectric devices and the importance of balancing both. We developed Landau FET-based voltage amplifiers (VA), including passive VA (PVA) and active VA (AVA), and compared to existing counterparts such as P(VDF-TrFE)-PVA and PZT-AVA, across low and high frequencies. The proposed PVA shows a 22.60% and 54.31% increase in amplification (ANC) at low and high frequencies, respectively, compared to P(VDF-TrFE)-PVA. The AVA exhibits a 17.86% increase in ANC at low frequencies compared to PZT-AVA but no ANC at higher frequencies due to symmetry-breaking. The Landau FET-based inverter shows a sharp state transition than the CMOS inverter, but this sharpness depends on tFE, N, and the degree of NC effect. The Landau FET-based fan-out-4 inverter with 7.7 nm tFE and N = 16 is 25.49% faster than the Si MOSFET inverter. Moreover, the impact of tFE and N on the performance of the proposed 5-stage ring oscillator (RO) is investigated concerning state-of-the-art CMOS RO counterparts. The 5-stage RO using Landau FET-based inverters showed (1.26–18.9) times higher oscillation frequency (fOSC) and (17.93–5.71) times reduced power dissipation compared to the existing CMOS ROs. Finally, we examined how process variations impact the fOSC in the proposed 5-stage Landau FET-based RO. The findings indicate a standard deviation of 0.39 GHz in the distribution of fOSC. These findings highlight the interplay between tFE scaling, N variations, and transient NC effect, advancing Landau FET-based devices for future NC electronics.

Exploring the impact of domain numbers on negative capacitance effects in ferroelectric Device-Circuit Co-Design

This paper explores the performance of Hf0.5Zr0.5O2 (HZO)-stacked negative capacitance field-effect transistor (NCFET) for possible beyond complementary metal–oxide–semiconductor (CMOS) technology. For the first time, we investigate the impact of ferroelectric (FE) domain numbers on the negative capacitance (NC) effect, energy dissipation, NC effect voltage window, polarization ramping rate, voltage amplification (ANC), and oscillation frequency of a 5-stage HZO-NCFET inverter-based ring oscillator (HZO-NCFET-RO). The results show that HZO-NCFET is suitable for low-voltage and high-speed applications, providing a significant increase in ANC concerning the conventional PZT-NCFET and P(VDF-TrFE)-NCFET. Our study suggests that the HZO intrinsic NC effect time scale is tiny and limited by the FE switching. We show that the switching time of HZO is ∼20 times faster than the traditional FE [Pb(Nb0.04Zr0.28Ti0.68)O3]. Finally, the proposed 5-stage HZO-NCFET-RO offers superior performance with a 26% higher oscillation frequency and a 94.42% reduction in power dissipation compared to standard 5-stage CMOS inverter-based RO. These findings highlight the potential of HZO-stacked NCFET as an alternative device for the future beyond-CMOS technology.

A thermally aware performance analysis of quantum cellular automata logic gates

<span lang="EN-US">The high-performance digital circuits can be constructed at high operating frequency, reduced power dissipation, portability, and large density. Using conventional complementary-metal-oxide-semiconductor (CMOS) design process, it is quite difficult to achieve ultra-high-speed circuits due to scaling problems. Recently quantum dot cellular automata (QCA) are prosed to develop logic circuits at atomic level. In this paper, we analyzed the performance of QCA circuits under different temperature effects and observed that polarization of the cells is highly sensitive to temperature. In case of the 3-input majority gate the cell polarization drops to 50% with an increase in the temperature of 18 K and for 5 input majority gate the cell polarization drops more quickly than the 3-input majority. Further, the performance of majority gates also compared in terms of area and power dissipation. It has been noticed that the proposed logic gates can also be used for developing simple and complex and memory circuits.</span>

Energy-efficient design techniques for LUT based adaptive digital pre-distorters

Energy-efficient design techniques for an adaptive Look-Up Table (LUT) based Digital Predistortion (DPD) system are presented. The proposed methods are simplification of the adaptation function, reduction of the memory hardware complexity and bypassing of the equalizer circuit. The equalizer circuit block is critical while the adaptation loop is enabled but need for this block while the loop is disabled is explored to reduce power dissipation. Three adaptation functions that require less complex hardware are presented. The system is modeled with Matlab-Simulink, then implemented using an FPGA and 130 nm ST-Silicon On Insulator (SOI) process. More than 33% of power saving is obtained by applying the proposed techniques and further power reductions are also possible by configuring the system.

Cluster-based test vector re-ordering for reduced power dissipation in digital circuits

Optimizing testing power is a paramount concern in modern digital circuit design, particularly as the intricacy of circuits continues to rise. This issue becomes even more pronounced with the scaling down of feature sizes due to advancements in process technology. The increase in testing power dissipation, beyond the regular operational state, raises red flags for both designers and test engineers. This paper introduces a novel cluster-based approach, shedding light on the efficient reordering of test vectors to mitigate the heightened switching activity. This technique aims to reduce the power consumption during testing, while still ensuring efficient error detection, maintaining the test period, and preserving the original order of the scan chain. Importantly, this reordering method does not introduce any additional area or test time overhead, minimizing the risks associated with these factors. The potential impact of this approach is demonstrated through concrete examples drawn from ISCAS’89 benchmark circuits. The results showcase a notable 11% reduction in switching activity, all while preserving fault coverage levels.

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications

This paper proposes a highly robust and low power flip-flop cell with complete double-node-upset (DNU) tolerance for aerospace applications. The proposed cell is constructed from a master latch and a slave latch. The master latch comprises two C-elements as well as one clock-controlled C-element; the slave latch is similar to the master but has an extra keeper to avoid high-impedance state of the output-level C-element. Simulation results demonstrate that the proposed cell can provide complete DNU-tolerance and also demonstrate that the proposed cell can reduce power dissipation by roughly 65% on average when compared with existing radiation-hardened flip-flop cells.

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Reduction of Power Losses in the Distribution System by Controlling Tap Changing Transformer using the PSO Algorithm

Energy is an essential commodity for everyone, with electrical energy being the most preferred form. Unfortunately, non-renewable energy resources are gradually depleting, and renewable energy sources take several years to establish. To mitigate this problem, technology has shifted from non-renewable energy sources to electrical devices and machines, including household appliances like washing machines and air conditioners. However, the generation of electricity is still inadequate to meet the growing demand. This leads to two critical issues: Excessive power loss and inadequate voltage stability, making it difficult for power distribution companies to ensure a consistent and reliable power supply. The objective of this study is to tackle the issue of reduction and minimization of power dissipation By employing the PSO technique, adjusting the transformer tap settings. The proposed approach uses the 14-bus system as a reference and calculates losses for this system using the backward-forward sweeping technique.

Bandwidth-Aware High-Efficiency Video Coding Design Scheme on a Multiprocessor System on Chip

H.265/high-efficiency video coding (HEVC) provides a multitude of video data compression to minimize data storage and data transmission while preserving video coding quality and ameliorating coding bit rates. However, HEVC encoder chips are frequently integrated into mobile multiprocessor system-on-chip (MPSoC) systems that adopt intelligent thermal and power management techniques for heat- and power-dissipation reductions. Consequently, the accessible coding bandwidth (CB) for HEVC encoder chip use is not fixed, and the compressed video data for data transmission within MPSoCs are restricted to time-altering wireless transmission bandwidths (TBs). Therefore, the proposed bandwidth-aware H.265/HEVC controller design solves the video coding problems of limited CB and TB by jointly using a machine-learning method and convex optimization. The ancillary experimental and implementation results demonstrate that the proposed CB-TB rate-coding distortion (CB-TB-R-D) algorithm modeling and the very large-scale integration (VLSI) hardware architecture are applicable for CB- and TB-constrained HEVC encoder design within MPSoC.

Novel PVT Resilient Low-Power Dynamic XOR/XNOR Design Using Variable Threshold MOS for IoT Applications

A variable threshold voltage hybrid evaluation network based dynamic XOR/XNOR gate is presented to reduce the parameters leakage power dissipation, dynamic power, and layout area compared to existing dynamic gates under similar delay time conditions. This study explores the impacts of process, supply voltage, and temperature changes on leakage power dissipation and dynamic power using Monte Carlo simulation. The Monte Carlo analysis demonstrates that leakage power dissipation and dynamic power reduction have significantly improved. Furthermore, when compared to hybrid type dynamic XOR/XNOR (N-type XOR/XNOR), the proposed design reduces leakage power and dynamic power consumption by 6.1% (54.0%) and 18.75% (35.0%), respectively. While the proposed design has a slight layout area penalty compared to a hybrid type dynamic XOR/XNOR, it offers the same amount of the layout area as a traditional N-type XOR/XNOR.

Ni-Silicide Ohmic Contacts on 4H-SiC Formed by Multi Pulse Excimer Laser Annealing

The formation of ohmic contacts by laser annealing approach is of great importance for SiC power devices, since it allows their fabrication on thin substrates, that is of crucial significance to reduce power dissipation. Ni silicide reaction under UV laser irradiation has been studied in detail with particular focus on single pulse approach, in order to describe the early stage of reaction process. The use of a multi pulse approach, for the formation of Ni silicide-based ohmic contacts by means of excimer laser annealing, has been investigated in this work. The reaction process has been characterized, as a function of number of pulses, by means of X-Ray Diffraction (XRD) and Transmission Electron Microscopy (TEM) analysis. Laser process simulations, formulated in the framework of phase field theory, have been performed in order to predict the evolution of material during reaction under annealing. Simulations show that reaction moves to Si-reach phases with the increasing on pulses, with a co-existence of Ni2Si and Ni3Si2 phases for the three pulses process. Moreover, simulations show critical differences, in terms of the uniformity of the distribution of the silicide phases along the film, between the single pulse and the multi pulses cases and the increasing of thickness of silicide phases with the pulse sequence. These predictions are in good agreement with the findings of XRD and TEM analyses. The electrical properties of the reacted layer have been evaluated on Schottky Barrier Diodes (SBD) devices, confirming the ohmic behaviour of multi pulse annealed samples.

Ultrafast High Voltage Pulse Generator Based on Power MOSFETs Delay Push-pull Structure

In this paper, an ultrafast high voltage pulse generator based on power MOSFETs delay push-pull structure is designed. The two complementary power MOSFETs are connected in the push-pull circuit and driven by the low-power MOSFETs separately. The output ultrafast high-voltage pulse amplitude is +30 V ~ -200 V, and the front edge and back edge times of the pulse are 5 ns and 4 ns, respectively. The width and frequency of the output pulse are controlled by the external trigger input signal. The shortest output pulse width is 12 ns and the maximum operating frequency is 100 kHz while the load is 10 pF. The delay conduction method of power MOSFETs is helpful to reduce power dissipation and improve the reliability of the circuit at a high operating frequency.

Improved reliability single loop single feed 7T SRAM cell for biomedical applications

Portable biomedical devices are born to reach a maximum number of people at an effective cost, and because of their small size and battery operation, the impact of portable medical devices is huge. For biomedical image processing devices, it is very important to store pixel information in embedded memory, because pixel values contain critical information about the image. For this critical information storage, most embedded memories consist of static random access memory (SRAM). SRAM, which stores critical information must have a high level of stability and reliability with low power dissipation. This paper proposes a single loop single-feed 7T (SLSF7T) SRAM cell that operates in the sub-threshold region (reducing the supply voltage to reduce power dissipation) and attains a high read static margin. To evaluate the read-and-write stability of the SRAM cell, the N-curve method is adopted in this work.The proposed SLSF7T SRAM cell design offers several improvements over existing Biomedical Transmission Gate 8T (BT8T) and 9T SRAM cells. Specifically, the SLSF7T SRAM cell design shows an increase in static voltage noise margin (SVNM) by 75.86% and 75.34%, reduction in delay by 37.86% and 58.52%, and also offers less leakage power dissipation by 72% and 23.29% as compared to the BT8T and 9T cells, respectively. Along with the low power and high stability, the other most significant feature of the proposed work is its area efficiency because the proposed memory cell only consists of 7 transistors, it requires only 1.1X area overhead compared to the conventional 6T memory cell. The calculated performance matrix of the proposed cell is the highest among the considered SRAM cells for compression. The proposed cell operates in the sub-threshold region and achieves the best performance parameters for memory design for biomedical devices and applications at a 300 mV supply voltage.

Power Loss Minimization in a Radial Distribution Network by Optimal Sizing and Placement of Energy Storage Units

It is possible to reduce distribution losses by strategically placing and sizing DG and BESS sources. Assuring low loss requires strategically placing the aforementioned devices; otherwise, the system may experience either under- or overvoltage. It is preferable to choose bus stations with less risk for loss. The proposed approach tries to pinpoint the optimal BESS size and placement to cut down on investment and operating expenses while still achieving the desired level of energy reduction. The development of optimisation algorithms for finding and scaling BESS units is the fundamental focus of this study. Two such strategies are being explored here: the Genetic Algorithm (GA) and the Ant Colony Optimization Algorithm (ACOA). The goal function, like the original issue, seeks to minimise system-wide power losses while adhering to specified levels of equality and inequality. This article explores the appropriate capacity and placement of the DGs in a 33-bus radial distribution grid to reduce power dissipations. Matlab code is used to perform a simulation, and the results are put to use gauging the method's sturdiness.