Drain Current Reduction Research Articles

Effects of Short-Term DC-Bias-Induced Stress on n-GaN/AlGaN/GaN MOSHEMTs With Liquid-Phase-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as a Gate Dielectric

This paper presents a comparative study of the degradation of dc characteristics and drain current collapse under dc-bias stress in passivated metal-oxide-semiconductor high-electron mobility transistor (MOSHEMT), unpassivated HEMT, and passivated HEMT devices. The Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> oxide thin film that is used as a gate dielectric and a passivation layer in MOSHEMTs is prepared by a simple, low-cost, and low-temperature liquid-phase deposition (LPD) technique. All devices are subjected to short-term dc-bias stress to investigate the reliability of the oxide and its passivation effect. In the case of MOSHEMTs and passivated HEMTs, the gradual reduction in drain current is found within 20-h drain-bias stress, which is apparently caused by the hot-electron injection and trapping in the buffer, and a barrier layer that is operated at a high drain voltage. However, faster degradation is found in unpassivated HEMTs, and some devices are permanently damaged due to the degradation of unpassivated surface states. Nonetheless, the current is partially recovered for all devices after gate stress, and no damage to the MOSHEMTs is observed. Therefore, it is believed that the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> thin film that is prepared through the LPD technique is effective as a gate dielectric and as a surface passivation layer in reducing device degradation during dc-bias stress and in diminishing the current collapse effect in MOSHEMTs.

Effects of the Local Environment on CNT-Based Nanoelectronics: Development of a Microenvironment Probe Station

In this study, we report the development of a microenvironment probe station capable of detecting the effect of small changes to the local environment around a carbon nanotube conduction channel. The microenvironment probe station is highly versatile and is used to characterize alterations in carbon nanotube field effect transistor electrical behavior in response to changes in temperature, gas species, infrared and ultraviolet light. All devices were electrically characterized in atmospheric, ultrahigh vacuum and oxygen-rich environments. The results suggest that devices could be changed from n-type at 1 x 10(-8) torr through an intermediate ambipolar state at 1 x 10(-4) torr to p-type at atmosphere solely by increasing the oxygen concentration. The average resistance of these carbon nanotube field effect transistors after annealing was observed to decrease by approximately 54% from their initial value under ultrahigh vacuum to their final value in the presence of pure oxygen while corresponding threshold voltages shifts were also observed. Illumination with infrared light resulted in a approximately 10% increase in drain current with an estimated response time <1 fs due to photon-induced electron-hole pair generation. Illumination with ultraviolet light resulted in approximately 5-15% reduction in drain current due to photon-induced desorption of oxygen adsorbate.

Threshold Voltage Control through Layer Doping of Double Gate MOSFETs

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an o therwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

Capacitor-less memory-cell fabricated on nanoscale unstrained Si layer on strained SiGe layer-on-insulator

We investigated the effect of the presence of strained SiGe layer inserted between unstrained Si and buried oxide layer and the Ge concentration in strained SiGe layer on the memory margin of capacitor-less memory-cell. We observed that memory margin of unstrained Si on strained SiGe-on-insulator capacitor-less memory-cells increases with the Ge concentration of the strained SiGe layer and obtained memory margin at the Ge concentration of 19 at% that was 3.2 times larger than that at the silicon-on-insulator capacitor-less memory-cell. This enhancement was due to the potential-barrier lowering increasing exponentially with the Ge concentration resulting from higher hole confinement in spite of the reduction in the saturated drain current.

Atomistic full-band simulations of silicon nanowire transistors: Effects of electron-phonon scattering

An atomistic full-band quantum transport simulator has been developed to study three-dimensional Si nanowire field-effect transistors in the presence of electron-phonon scattering. The nonequilibrium Green's function (NEGF) formalism is solved in a nearest-neighbor $s{p}^{3}{d}^{5}{s}^{\ensuremath{\ast}}$ tight-binding basis. The scattering self-energies are derived in the self-consistent Born approximation to inelastically couple the full electron and phonon energy spectra. The band dispersion and the eigenmodes of the confined phonons are calculated using a dynamical matrix that includes the bond and the angle deformations of the nanowires. The optimization of the numerical algorithms and the parallelization of the NEGF scheme enable the investigation of nanowire structures with diameters up to 3 nm and lengths over 40 nm. It is found that the reduction in the device drain current, caused by electron-phonon scattering, is more important in the ON state than in the OFF state of the transistor. Ballistic transport simulations considerably overestimate the device ON currents by artificially increasing the charge injection mechanism at the source contact.

Water-Related Instabilities in Pentacene Thin-Film Transistors

We have analyzed the hysteresis of the transfer characteristics of pentacene thin-film transistors (TFTs) measured under different environmental conditions (vacuum, oxygen, dry nitrogen, air and nitrogen with different relative humidities). The results showed that, whereas the characteristics in dry atmospheres are quite stable, the hysteresis increases with the percentage of moisture, indicating that adsorbed water is the main cause of the environmental instability in pentacene TFTs. In addition, transient current experiments have been carried out in air. Through these measurements, we have been able to evaluate a characteristic time of drain current reduction of several seconds. These results indicate that the environmental instability is not simply related to charge trapping in localized gap states and slower phenomena should also be considered.

SiC Lateral Trench JFET for Harsh-Environment Wireless Systems

SiC Lateral Trench JFET (LTJFET) technology is demonstrated as a promising candidate for use in high-temperature wireless telemetry systems. 4H-SiC LTJFETs were designed, fabricated and characterized for DC, and small-signal AC and RF performance at different case temperatures. Four-fold drain current reduction was observed at 460°C as compared to RT measurements. The measured threshold voltage shift was less than 2.3 mV/°C from 21°C to 460°C. A simple common source amplifier built using a fabricated device demonstrated stable small-signal AC performance after 100 hrs of operation at 450°C. Small-signal RF measurements were carried out on the packaged devices at different temperatures. GMax above 8 dB was measured over the L-band frequency range at RT. The average degradation of small-signal power gain measured at f=250 MHz did not exceed 0.0125 dB/ °C over the temperature ranging from 21°C to 365°C.

Current Collapse Characteristic of AlGaN/GaN MIS-HEMT

We investigated the current collapse characteristics of the fabricated MIS-HEMT with the SiO2, SiN and high-k gate insulator. TiO2 was employed as the high-k material. We found the significant drain current change in the switching characteristic when the insulator changes. The SiN MIS-HEMT showed good switching characteristic. On the other hand, the MIS-HEMTs with oxide insulator film showed large drain current reduction. We considered that the degradation of the switching characteristic is due to the current collapse.

Effects of a Thermal CVD SiN Passivation Film on AlGaN/GaN HEMTs

In AlGaN/GaN high electron mobility transistors (HEMTs), drain current reduction by current collapse phenomenon is a big obstacle for a high efficient operation of power amplifier application. In this study, we investigated the effects of SiN passivation film quality on the electrical characteristics of AlGaN/GaN HEMTs. First, we conducted some experiments to investigate the relationship between electrical characteristics of AlGaN/GaN HEMTs and various conditions of SiN passivation film by plasma enhanced chemical vapor deposition (PE-CVD). We found that both gate current leakage and current collapse were improved simultaneously by SiN passivation film deposited by optimized condition of NH3 and SiH4 gas flow. It is found that the critical parameter in the optimization is a IN-H/ISi-H ratio measured by Fourier transforms infrared spectroscopy (FT-IR) spectra. Next, a thermal CVD SiN was applied to the passivation film to be investigated from the same point of view, because a thermal CVD SiN is well known to have good quality with low hydrogen content and high IN-H/ISi-H ratio. We confirmed that the thermal CVD SiN passivation could improve much further both of the gate leakage current and the current collapse in AlGaN/GaN-HEMTs. Furthermore, we tried to apply the thermal CVD SiN to the gate insulator in MIS (Metal Insulator Semiconductor) structure of AlGaN/GaN HEMTs. The thermal CVD SiN passivation was more suitable for the gate insulator than PE-CVD SiN passivation in a view of reducing current collapse phenomena. It could be believed that the thermal CVD SiN film is superior to the PE-CVD SiN film to achieve good passivation and gate insulator film for AlGaN/GaN HEMTs due to the low hydrogen content and the high IN-H/ISi-H ratio.

Circuit level prediction of device performance degradation due to negative bias temperature stress

A circuit level methodology for predicting performance degradations due to negative bias temperature stress is developed in this paper. Degradation mechanism is discussed based on experimental observations. Then, models that consist of a threshold voltage shift and a drain current reduction are developed based on the degradation mechanism. The developed models are implemented into a compact MOSFET model so that we can directly link the local degradation of pMOSFETs’ electrical characteristics to the total circuit performances. The validity of the developed models is confirmed by the good agreement in simulated and measured results of I– V characteristics of pMOSFET in all the transistor working region before and after negative bias temperature stress. Then, circuit performance prediction is carried out for the stressed 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between the experimental results and predicted results are obtained.

Temperature dependent microwave performance of AlGaN/GaN high-electron-mobility transistors on high-resistivity silicon substrate

The influence of temperature (− 50 °C to + 200 °C) was studied on the DC and microwave characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) on high resistivity Si substrate for the first time. The AlGaN/GaN HEMTs exhibited a current-gain cut-off frequency ( f T) of 11.8 GHz and maximum frequency of oscillation ( f max) of 27.5 GHz. When compared to room temperature values, about 4% and 10% increase in f T and f max and 23% and 39.5% decrease in f T and f max were observed when measured at − 50 °C and 200 °C, respectively. The improvement of I D, g m f T, and f max at − 50 °C is due to the enhancement of 2DEG mobility and effective electron velocity. The anomalous drain current reduction in the I– V curves were observed at low voltage region at the temperature ≤ 10 °C but disappeared when the temperature reached ≥ 25 °C. A positive threshold voltage ( V th) shift was observed from − 50 °C to 200 °C. The positive shift of V th is due to the occurrence of trapping effects in the devices. The drain leakage current decreases with activation energies of 0.028 eV and 0.068 eV. This decrease of leakage current with the increase of temperature is due to the shallow acceptor initiated impact ionization.

Improvement of Short Channel Mobility and Operational Stability of Pentacene Bottom-Contact Transistors with a Sulfuric Acid and Hydrogen Peroxide Mixture (SPM) Treatment of Au Electrodes

ABSTRACTWe report a reduction in the contact resistance between pentacene and Au source/drain electrodes of organic field effect transistors (OFETs) with bottom-contact structure. By immersing the Au electrodes in a sulfuric acid and hydrogen peroxide mixture (SPM), the injection barrier between the Au electrodes and pentacene was lowered by approximately 0.2 eV and the contact resistance significantly decreased. The fabricated bottom-contact OFETs revealed a field-effect mobility of more than 0.66 cm2/Vs at a channel length ranging from 3 to 30 μm, which is comparable to that of top-contact OFETs with a 50 μm channel length. The transfer characteristics of the OFET with the SPM treatment were stable even after 44days storage in air under room illumination without any passivation. Moreover, the drain current reduction due to threshold voltage (Vth) shift under continuous application of gate voltage quickly recovered toward the original value with unloading of gate voltage.

Studies of AlGaN/GaN high-electron-mobility transistors on 4-in. diameter Si and sapphire substrates

The AlGaN/GaN high-electron-mobility transistors (HEMTs) fabrication and its dc characteristics have been performed on both 4-in. diameter Si and sapphire substrates. Due to the high crystalline quality with one order low dislocation density of GaN on sapphire substrate, better 2DEG mobility with high values of drain current density (511 mA/mm) and extrinsic transconductance (198 mS/mm) were observed. Large OFF-state breakdown voltage (BV gd) with low gate leakage current was observed on sapphire-based HEMTs. Though the sapphire-based HEMTs show better characteristics than Si-based HEMTs, the thermal dissipation from the device is not good enough. The low thermal resistance of Si-based HEMTs leads the existence of high ON-state BV gd. This has been confirmed by measuring the device surface temperature ( T D) by infrared microscope camera. Higher value of T D = 74 °C at V DS = 20 V and V GS = +1.5 V was observed on sapphire-based single finger 400-μm-wide and 2-μm-gate-length HEMTs when compared to the HEMTs on Si ( T D = 41 °C). The measured T D has been directly correlated with the measured drain current reduction ( I Dreduc.) due to self-heating. About 83% of high rate of increase in temperature by self-heating was observed on sapphire-based HEMTs when compared to Si-based HEMTs. The device thermal impedance ( R th) of Si- and sapphire-based AlGaN/GaN HEMTs are 44 and 139 °C/W, respectively. The ratio of R thSi/ R thSapp = 0.30 obtained from our studies is consistent with the reported values of 0.297. The 4-in. diameter Si has been shown to be a viable alternative substrate for low-cost high-power operating GaN HEMTs.

Impact of Single Charge Trapping in Nano-MOSFETs—Electrostatics Versus Transport Effects

In this paper, using Monte Carlo (MC) simulations featuring ab initio Coulomb scattering, we study the impact of Coulomb scattering from a single trapped electron on the magnitude of the corresponding drain-current reduction in a series of well scaled n-channel nano-MOSFETs. Through a careful comparison with drift-diffusion (DD) simulations that only capture the electrostatic effects associated with the trapped charge, we were able to demonstrate the specific contribution of the scattering. The simulations are performed at low drain bias for MOSFETs with channel lengths of 30, 20, and 10 nm, respectively. Compared to the DD results, the MC simulations show significant additional reduction in drain current associated with the scattering from the trapped electron. The scattering related percentage reduction in the current increases with the increase of the gate voltage toward strong inversion conditions. The velocity distributions in the presence of the trapped charge at various gate conditions are carefully analyzed in order to explain the magnitude of the observed effect.

MOSFET drain current reduction under Fowler–Nordheim and channel hot carrier injection before gate oxide breakdown

We studied the degradation of MOSFETs with 3.2 nm gate oxide under Fowler–Nordheim and channel hot carrier injection, focusing on the evolution of the characteristics before the occurrence of any oxide breakdown, soft or hard. In order to assess the damage and understand its origin, we monitored different parameters: transfer and output characteristics, gate leakage, charge pumping current, and low-frequency noise. After both types of stress, the MOSFETs showed a substantial drop in the transconductance accompanied by a moderate increase in the threshold voltage and a reduction in the drain saturation current. At the same time we observed the increase of the gate leakage current, charge pumping current, and 1/ f noise. We interpreted these results in terms of slow and fast interface-trap creation in the gate oxide, highlighting the correlation between the defects responsible for the different degradations observed. In particular, we linked the SILC generation to the low frequency noise increase. Finally, we tried to recover the damage by injecting electrons across the oxide at moderate field, reducing only SILC and 1/ f noise in this way.

Carrier injection efficiency for the reliability study of 3.5–1.2 nm thick gate-oxide CMOS technologies

The hot carrier (HC) reliability has been investigated in MOSFETs with ultra-thin SiO 2 gate-oxide ranging from T ox=3.5 to 1.2 nm and in high speed CMOS technologies in order to identify the worst-case of HC injections. Distinctions are obtained between the influence of the T ox thinning and the shrink of the gate-length with L G ranging from 0.25 to 0.1 μm. Results show that the worst-case of HC damage can be different from the bias condition of the maximum substrate current (IB) in N-channel devices and of the hot electron (HE) injections in P-channel devices with the T ox and L G margin. It is shown that the interface trap generation (Δ N it) has become the main damage mechanism at long term with the use of the correlation between charge pumping analysis and drain current reduction. We focus on the hole injection efficiency, the extension of the degraded region (Δ L) with the L G reduction and the influence of the carrier energy which all participate to the degradation of ultra-thin gate-oxide MOSFETs submitted to carrier injections.

Comparison of degradation modes in 1.2–2.1 nm thick SiO 2 oxides submitted to uniform and hot carrier injections in NMOSFETS

In this work, we have studied the evolution of the electrical properties of 1.2–2.5 nm-thick SiO 2 oxides in N-channel metal–oxide–semiconductor field effect transistors submitted to either uniform electron injections in the direct tunneling regime or localized channel hot carrier injections. The degradation of the oxide is investigated through the classical electrical parameter set of the transistor, the gate leakage current, and charge pumping measurements. Constant current stresses at J inj=34 mA/cm 2 did not induce any damage. In contrast, constant voltage stresses at V G=3.5 V led to an increase up to a factor of 10 in the gate current, I G, in the [−0.4,−1 V] range, while small variations of transistor parameters were detected. Hot carrier stresses were performed in 50/1 μm transistors at the condition of maximum of substrate current for drain voltages, V D=3.5 and 4 V, with or without a substrate bias. We find an increase in the interface state density measured by charge pumping practically independent of the oxide thickness for times >100 s, which is correlated to transconductance and drain current reduction depending on substrate bias. But no correlation is found with the evolution of the gate current, which indicates that the I G increase is not directly linked here to the increase in interface state density revealed by charge pumping. An explanation of this apparent contradiction using the different energy levels and the localization of the defects induced in both cases is proposed.

Role of scattering in nanotransistors

We model the influence of scattering along the channel and extension regions of dual gate nanotransistor. It is found that the reduction in drain current due to scattering in the right half of the channel is comparable to the reduction in drain current due to scattering in the left half of the channel, when the channel length is comparable to the scattering length. This is in contrast to a popular belief that scattering in the source end of a nanotransistor is significantly more detrimental to the drive current than scattering elsewhere. As the channel length becomes much larger than the scattering length, scattering in the drain-end is less detrimental to the drive current than scattering near the source-end of the channel. Finally, we show that for nanotransistors, the classical picture of modeling the extension regions as simple series resistances is not valid.

Analysis of the anomalous drain current characteristics of halo MOSFETs

An analytical model for the anomalous behavior of the halo or pocket implanted MOSFETs is presented for both strong and weak inversion operation. Even though most of the drain current reduction due to the pocket implantation can be explained by the effective threshold voltage of halo MOSFETs, a further decrease has been observed that can be attributed to the effects of the halo implants on the effective mobility as well as threshold voltage of these devices. Taking into account the effect of the regionally distinctive distributions of the physical quantities related to the charge transport, a simple drain current model suitable for implementation in circuit simulators is developed. The presented analytical model is shown to agree well with 2D simulations and experiments. The reduced dependency of the subthreshold current on the gate length is also explained.

Hot electron effects on Al/sub 0.25/Ga/sub 0.75/As/GaAs power HFET's under off-state and on-state electrical stress conditions

This work shows a detailed comparison of the degradation modes caused by off-state and on-state room temperature electrical stress on the DC characteristics of power AlGaAs/GaAs heterostructure field effect transistors (HFET's) for X- and Ku-band applications. The devices are stressed under DC bias conditions that result in electron heating and impact ionization in the gate-drain region. Incremental stress experiments carried out at gate-drain reverse currents up to 3.3 mA/mm (for a total of more than 700 h) show a remarkably larger degradation for the off state stress, due to more pronounced electron heating at any fixed value of gate reverse current. This represents an important piece of information for the reliability engineer when it comes to designing the accelerated stress experiments for hot electron robustness evaluation. The degradation modes observed, all of a permanent nature, include threshold voltage and drain resistance increase and drain current and transconductance reduction.