Reduction In Critical Path Delay Research Articles

SRAM Compilation and Placement Co-Optimization for Memory Subsystems

Co-optimization for memory bank compilation and placement was suggested as a way to improve performance and power and reduce the size of a memory subsystem. First, a multi-configuration SRAM compiler was realized that could generate memory banks with different PPA by splitting or merging, upsizing or downsizing, threshold swapping, and aspect ratio deformation. Then, a timing margin estimation method was proposed for the memory bank based on placed positions. Through an exhaustive enumeration of various configuration parameters under the constraint of timing margins, the best SRAM memory compilation configuration was found. This method could be integrated into the existing physical design flow. The experimental results showed that this method achieved up to an 11.1% power reduction and a 7.6% critical path delay reduction compared with the traditional design method.

Digital Image Blending by Inexact Multiplication

Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and product bits. We considered many 8-bit digital images for blending and the blended images obtained using exact and inexact multipliers are shown, which demonstrates the usefulness of inexact multiplication for image blending. For 8 × 8 image blending, one of our inexact array multipliers viz. IAM01-VC8 was found to achieve 63.3% reduction in area, 21% reduction in critical path delay, 72.3% reduction in power dissipation, and 78.1% reduction in energy compared to the exact array multiplier. In addition, IAM01-VC8 achieved 60.6% reduction in area, 9.7% reduction in critical path delay, 64.7% reduction in power dissipation, and 68.1% reduction in energy compared to the high-speed exact 8 × 8 multiplier that was automatically synthesized using a logic synthesis tool. The exact and inexact multipliers were physically realized using 32/28 nm CMOS process technology.

High-Speed and Energy-Efficient Carry Look-Ahead Adder

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal

Low-complexity, high-speed and re-configurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of acquired seismic signal in real-time seismic-alert-system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (LOs) and logic depths (LDs) in digital FIR filter. In this brief, a novel matrix grouped CSE (MCSE) algorithm has been proposed which outperforms the existing CSE algorithms in terms of LOs and LDs minimization. Moreover, a new half-unit biased (HUB) based rounding technique is incorporated in the proposed design to reduce the truncation error while maintaining low-complexity and the cut-set retiming technique is employed to reduce the critical-path-delay (CPD). Two hardware efficient FIR filter architectures (I and II) involving the proposed canonical signed digit (CSD) based MCSE algorithm, HUB rounding and cut-set retiming approach have been presented. Further, the architecture II represents a hardware efficient realization of a reconfigurable FIR filter. The hardware implementation of the architectures is performed on both FPGA and ASIC platforms. The hardware implementation of the proposed architecture I yields more than 25%, 49%, 38%, 36% and, 31% reduction in LOs, CPD, effective latency, area-delay-product (ADP) and, power-delay-product (PDP), respectively, over the state-of-the-art CSE based architectures. Whereas the reconfigurable architecture II exhibits nearly 48%, 12% and, 13% reduction in CPD, ADP and, PDP over the counterpart.

Efficient VLSI architecture of 3D discrete transformation

Discrete transforms are used in many signal processing applications such as audio compression, image compression, video compression, high efficiency video coding (HEVC), and so on. This paper proposes a generic VLSI architecture for performing (N×N×N)-point discrete transformation. This proposed generic architecture can be used to perform the 3D discrete transformations such as Discrete Cosine Transform (DCT), Discrete Sine Transform (DST), Discrete Hartley Transform, Integer Discrete Cosine Transform (Integer DCT), Discrete Hadamard Transform, and Discrete Walsh Transform. Also, this (N×N×N)-point discrete transformation’s proposed architecture is to perform ⌊N2i⌋ numbers of (2i×2i×2i)-point discrete transforms in parallel, where i is varied from 2, 3, 4, …log2N for Discrete Hartley Transform, i=3 for DCT/DST, and i=2,3,4,5,6 for Integer DCT/Discrete Walsh/Discrete Hadamard Transforms. Also, our proposed architecture eliminates the requirement of larger storage buffer in between the row, column, and temporal processes. The trade-off in our proposed design is the number of cycles to complete the operation. All the existing and proposed techniques are implemented with 45 nm CMOS technology using Cadence. The synthesis results show that our proposed architecture achieves 73% of reduction in critical path delay as compared with the parallel Butterfly architecture based 3D-DCT.

Approximate Array Multipliers

This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.

Memory-efficient architecture for FrWF-based DWT of high-resolution images for IoMT applications

This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost memory-constrained sensor nodes used in visual sensor networks (VSN) or Internet of Multimedia Things (IoMT). The main feature of the proposed architecture is the novel data scanning technique that makes memory requirement independent of the image size. The proposed architecture needs only (30S) words of memory, where S is the number of parallel processing units and a critical path delay (CPD) equal to the delay of a multiplier (Tm). Furthermore, a multiplierless version of this architecture is also proposed which reduces the CPD to Ta<Tm (where Ta is the delay of an adder). In order to evaluate their effectiveness, the proposed architectures are coded in HDL and implemented on same FPGA board. Their performance is also compared with other state-of-the-art low memory DWT architectures. The experimental results show the superiority of the proposed architectures in terms of memory and CPD compared to existing DWT architectures. Moreover, the reduction in CPD to Ta indicates that the operating frequency can be scaled up by several factors and can be chosen depending upon the application. Compared to one of the best state-of-the-art DWT architecture, proposed multiplierless architecture (with S = 4) needs 57.37% less LUT’s and 64.39% less flip-flops for HR image of dimension 2048 × 2048. Moreover, the proposed architecture needs no LUTRAM and DSP, whereas the existing architecture requires 3264 LUTRAM and 24 DSP’s. Thus the proposed multiplierless architecture is superior to the existing state-of-the-art architecture and is suitable for IoMT/VSNs.

Decisive structures for multirate FIR filter incorporating retiming and pipelining schemes

PurposeVery large-scale integration (VLSI) digital signal processing became very popular and is predominantly used in several emerging applications. The optimal design of multirate filter with improvement in performance parameters such as less area, high speed and less power is the challenging task in most of the signal processing applications. This study aims to propose several effective multirate filter structures to accomplish sampling rate conversion.Design/methodology/approachThe multirate filter structures considered in this work are polyphase filter and coefficient symmetry-based finite impulse response filter. The symmetry scheme particularly brings down the complexity to significant extent. To bring improvement in speed, delay registers are inserted at appropriate path with the help of pipelining and retiming scheme.FindingsIn this paper, the three tasks have been considered. First, the polyphase coefficient symmetry and modified polyphase (MP) structure is designed. Second, the pipelining is applied to the polyphase structure and the obtained results are compared with the polyphase structure. In third, retiming is applied to the polyphase structure and the performance comparison is carried out. The structures are realized for various orders, and the comparative analysis is carried out with the filter order N = 12, 30, 42, 8, 11 and 24 and the results are stated. The performance of all the accomplished structures is analyzed using Altera Quartus with the family cyclone II, device EP2C70F672C6. The results show that the multirate filter using pipelining and retiming offers better performance when examining with the conventional structures. Retimed and pipelined MP structure achieves a speed enhancement of about 33.81% when examining with the conventional polyphase (CP) structure with retiming and pipelining for N = 24 and M = 5. Likewise, the 2/3 structure of pipelined coefficient symmetry approach offers area reduction of about 54.76% over 2/3 structure of pipelined polyphase approach for N = 30 with little reduction in power. The fine grain pipelined and retimed MP structure with N = 11 and M = 3 avails critical path delay reduction of about 28.15% when examining with the corresponding fine grain pipelined and retimed CP structure.Originality/valueThe proposed distinct structures offer better alternative to conventional structures because of the symmetric coefficients, performance enhancement using pipelining and retiming based rate conversion structures. The suggested structures can be used for achieving different rates in software radios.

Low Memory Architectures of Fractional Wavelet Filter for Low-Cost Visual Sensors and Wearable Devices

This paper proposes a low memory architecture of fractional wavelet filter for computing two-dimensional discrete wavelet transform of gray-scale images. The proposed architecture uses a data scanning order which mainly contributes to memory reduction. A multiplierless version of the proposed architecture is also designed to reduce the critical path delay equal to the delay of an adder. The proposed architectures and an existing low memory discrete wavelet transform architecture are implemented on the same field programmable gate array board and their performance are compared for different image resolutions. The results show that the proposed architectures (with and without multipliers) uses lesser basic blocks, such as look-up tables (about 85-94% less), flip-flops (about 85-90% less), consumes lesser dynamic power (about 58-75% less), and results in critical path delay reduction of (about 23-77%) compared to one of the best existing low memory discrete wavelet transform architecture for images of $1024\times {1024}$ pixels. These advantages are achieved in addition to reduction in memory requirement over the existing state-of-the-art architectures. Thus, the proposed architectures are viable options for calculating discrete wavelet transform coefficients of gray-scale images on low-cost memory-constrained platforms like visual sensors/wearable devices and Internet of things.

Analysis of effectiveness of power on refined numerical models of floating point arithmetic unit for biomedical applications

“The technology defined today might be redefined tomorrow”- from the quotes, in the modern era redefining the architecture with the optimization of area, delay and reduction of power is focused more than fixed models. This paper describes the floating point arithmetic unit and insists the importance of it, in real time signal processing. The present trends of portable devices for medical applications need occupancy of smaller area with long span time life of battery. The bio medical signals are converted into IEEE 754 format as BIF. Hence it is easily analyzed in FPGAR devices and also this work insists the importance of redefining the architecture with reduction of critical path delay. The FPU arithmetic unit has the blocks to perform the computations like addition, Multiplication and division operation. The main architecture is constructed using top level design with individual blocks defined as a part of it. The floating point unit defined with modern FPGAR (Reconfigurable FPGA) increase the speed of computation and enables the flexibility and adopted to the hardware reconfigurable models. A 32 bit representation of IEEE 754 results of FPU is stored in the data storage and this process optimize the critical path between blocks. The way its programmed consumes lower level of power consumption in the range of 50.4 nw and delay of 25.2 ns and also modern adder structure with 6T type was used to implement the intermediate blocks of multiplier in FPU block as part of computing partial products. By this process of FPU redefining, reduce the number of slice to 206 and increase the operating frequency of 46.12 MHz.

The FPOA, a Medium-grained Reconfigurable Architecture for High-level Synthesis

In this article, we present a novel type of medium-grained reconfigurable architecture that we term the Field Programmable Operation Array (FPOA). This device has been designed specifically for the implementation of HLS-generated circuitry. At the core of the FPOA is the OP-block. Unlike a standard LUT, an OP-block performs multi-bit operations through gate-based logic structures, translating into greater speed and efficiency in digital circuit implementation. &lt;?tight?&gt;Our device is not optimized for a specific application domain. Rather, we have created a device that is optimized for a specific circuit structure, namely those generated by HLS. This gives the FPOA a significant advantage as it can be used across all application domains. In this work, we add support for both distributed and block memory to the FPOA architecture. Experimental results show up to a 13.5× reduction in logic area and a 9.5× reduction in critical path delay for circuit implementation using the FPOA compared to a standard FPGA.

Hardware Optimized and Error Reduced Approximate Adder

This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.

Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures

Single constant multiplication (SCM) and multiple constant multiplications (MCM) are among the most popular schemes used for low-complexity shift-add implementation of finite impulse response (FIR) filters. While SCM is used in the direct form realization of FIR filters, MCM is used in the transposed direct form structures. Very often, the hybrid form FIR filters where the sub-sections are implemented by fixed-size MCM blocks provide better area, time, and power efficiency than those of traditional MCM and SCM based implementations. To have an efficient hybrid form filter, in this paper, we have performed a detailed complexity analysis in terms of the hardware and time consumed by the hybrid form structures. We find that the existing hybrid form structures lead to an undesirable increase of complexity in the structural-adder block. Therefore, to have a more efficient implementation, a variable size partitioning approach is proposed in this paper. It is shown that the proposed approach consumes less area and provides nearly 11% reduction of critical path delay, 40% reduction of power consumption, 15% reduction of area-delay product, 52% reduction of energy-delay product, and 42% reduction of power-area product, on an average, over the state-of-the-art methods.

High Performance Error Tolerant Adders for Image Processing Applications

In this paper, we proposed High Performance Error Tolerant Adders (HPETA) which have an efficient design and quality metrics for inexact computing applications. To achieve high performance, Multiplexer Based Approximate Full Adders (MBAFA) are proposed in the inaccurate part of the HPETA design. High speed, energy and area efficiency have been achieved by the critical path delay reduction and the number of gate-level logic reduction. The performances of the proposed MBAFA and HPETA are investigated by comparing its speed, area, power and accuracy parameters with those of other existing error tolerant adder structures. The investigation of these designs is performed in the Cadence Encounter software using the Application Specific Integration Circuits (ASIC) TSMC 90-nm technology library. From the Simulation results, the proposed MBAFA-I based HPETA-I adder exhibits high speed, area efficiency, low power consumption, less Area-Delay Product (ADP) and 56.25%, 47.98%, 37.58%, 34.03%, 39.32% lesser Power-Delay Product (PDP) than the existing conventional CSLA, SAET-CSLA, ETCSLA, HSETA, HSSSA, respectively.

Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector

Corner detection plays an essential role in many computer vision applications, e.g., object recognition, motion analysis and stereo matching. Several hardware implementations of corner detection algorithms have been previously reported to meet the real-time requirements of such applications. However, most of the reported implementations adopt similar computational flow which limit their potential for further area-time optimizations. In this paper, we propose a novel hardware design for the FAST corner detector, which unrolls the data-path to perform partial evaluation of multiple corners in a pipelined manner. We then apply logic folding that maximizes the design regularity of the unrolled data-path for resource sharing of the combinational operations. We show that the proposed design on FPGA leads to 20% reduction in critical path delay and about 39% reduction in area-delay product compared to a previously reported architecture. The real-time capability of the proposed FAST corner detectors is demonstrated on the TERASIC DE2i-150 FPGA development kit.

Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units

Three-dimensional stacked integrated circuits (3D-SICs) have been expected to overcome the limitations of conventional two-dimensional (2-D) implemented circuits. Since a stacking strategy affects the performance and the power consumption of 3D-SICs, this paper examines two stacking strategies for designing the 3-D stacked floating-point fused multiplyadd (FP-FMA) module which contains four FP-FMA units. Experimental results show that a coarse-grain stacking strategy is suitable for reducing critical path delay of the 3-D stacked FP-FMA module. On the other hand, a fine-grain stacking strategy is suitable for reducing power consumption. The 3-D stacked FP-FMA module which is designed based on a fine-grain stacking strategy achieves an 8.4% critical path delay reduction and an 18% average power reduction compared with the 2-D implementation.

Efficient Realization of BCD Multipliers Using FPGAs

In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.

Healing of DSP Circuits Under Power Bound Using Post-Silicon Operand Bitwidth Truncation

Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For digital signal processing (DSP) hardware, variations in circuit parameters can significantly affect the quality of service (QoS). Existing post-silicon calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, frequency, or body bias and typically incur large delay or power overhead. This paper presents a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least significant bits. Hence, truncation of these bits, by setting them at constant values, can effectively reduce the delay of a unit, thereby avoiding delay failures. The proposed technique is applied to two common DSP blocks, namely discrete cosine transform (DCT) and finite impulse response (FIR) filter. Simulation results show significant reduction in critical path delay along with a graceful degradation in the QoS. They also show large improvement in manufacturing yield (41.6%) with up to 5X savings in power compared to existing approaches such as voltage scaling and body biasing.

Area-Efficient Configurable High-Throughput Signal Detector Supporting Multiple MIMO Modes

This paper presents a low-complexity, high-throughput, and configurable multiple-input multiple-output (MIMO) signal detector design solution targeting the emerging Long-Term-Evolution-Advanced (LTE-A) downlink. The detector supports signal detection of multiple MIMO modes, which are spatial-multiplexing (SM), spatial-diversity (SD), and space-division-multiple-access (SDMA). Area-efficiency is achieved by algorithm and architecture co-design where low-complexity, near-maximum-likelihood (ML) detection algorithms are proposed for these three MIMO modes respectively while keeping in mind that the operations can be reused among different modes. A parallel multistage VLSI architecture is accordingly developed that achieves high detection throughput and run-time reconfigurability. To further improve the implementation efficiency, the detector also adopts an orthogonal-real-value-decomposition (ORVD) aided candidate-sharing technology for low-cost partial Euclidean distance calculation and a distributed interference cancelation scheme for a critical path delay reduction. The proposed multi-mode MIMO detector has been designed using a 65-nm CMOS technology with a core area of 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (the equivalent gate-count is 88.2 K), representing a 22% less hardware-resource use than the state of art in the open literature. Operating at 1.2-V supply with 165-MHz clock, the detector achieves a 1.98 Gb/s throughput when configured to the 4 × 4 64-QAM spatial-multiplexing mode. The corresponding normalized energy consumption is 51.8 pJ per bit detection.

Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m)

Radiation induced transient faults like single event upsets (SEU) and multiple event upsets (MEU) in memories are well researched. As a result of the technology scaling, it is observed that the logic blocks are also vulnerable to malfunctioning when they are deployed in radiation prone environment. However, the current literature is lacking efforts to mitigate such issues in the digital logic circuits when exposed to natural radiation prone environment or when they are subjected to malicious attacks by an eavesdropper using highly energized particles. This may lead to catastrophe in critical applications such as widely used cryptographic hardware. In this paper, novel dynamic error correction architectures, based on the BCH codes, is proposed for correcting multiple errors which makes the circuits robust against radiation induced faults irrespective of the location of the errors. As a benchmark test case, the finite field multiplier circuit is considered as the functional block which can be the target for major attacks. The proposed scheme has the capability to handle stuck-at faults that are also a major cause of failure affecting the overall yield of a nano-CMOS integrated chip. The experimental results show that the proposed dynamic error detection and correction architecture results in 50% reduction in critical path delay by dynamically bypassing the error correction logic when no error is present. The area overhead for the larger multiplier is within 150% which is 33% lower than the TMR and comparable to 130% overhead of single error correcting Hamming and LDPC based techniques.