Efficient VLSI architecture of 3D discrete transformation

Abstract

Discrete transforms are used in many signal processing applications such as audio compression, image compression, video compression, high efficiency video coding (HEVC), and so on. This paper proposes a generic VLSI architecture for performing (N×N×N)-point discrete transformation. This proposed generic architecture can be used to perform the 3D discrete transformations such as Discrete Cosine Transform (DCT), Discrete Sine Transform (DST), Discrete Hartley Transform, Integer Discrete Cosine Transform (Integer DCT), Discrete Hadamard Transform, and Discrete Walsh Transform. Also, this (N×N×N)-point discrete transformation’s proposed architecture is to perform ⌊N2i⌋ numbers of (2i×2i×2i)-point discrete transforms in parallel, where i is varied from 2, 3, 4, …log2N for Discrete Hartley Transform, i=3 for DCT/DST, and i=2,3,4,5,6 for Integer DCT/Discrete Walsh/Discrete Hadamard Transforms. Also, our proposed architecture eliminates the requirement of larger storage buffer in between the row, column, and temporal processes. The trade-off in our proposed design is the number of cycles to complete the operation. All the existing and proposed techniques are implemented with 45 nm CMOS technology using Cadence. The synthesis results show that our proposed architecture achieves 73% of reduction in critical path delay as compared with the parallel Butterfly architecture based 3D-DCT.