Reduced Supply Voltage Research Articles

Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Signal integrity has become a major problem in digital IC design. One cause is device scaling that results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. This paper introduces both a novel on-chip decoupling capacitance methodology and active noise cancellation (ANC) structure. The decoupling methodology focuses on quantification and location. The ANC structure, with an area of 50 <formula formulatype="inline"><tex Notation="TeX">$\mu {\hbox {m}} \times\,55 \mu{\hbox {m}}$</tex></formula>, uses decoupling capacitance to sense noise and inject a proportional current into <formula formulatype="inline"><tex Notation="TeX">$V _{\rm SS}$</tex></formula> as a method of reduction. A chip has been designed and fabricated using TSMC's 90-nm technology. Measurements show that the decoupling methodology improved the average voltage headroom loss by 17% while the ANC structure improved the average voltage headroom loss by 18%. </para>

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size of MIM capacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nm CMOS process with a maximum discrepancy of less than 5%.

Applications of impact-ionization metal–oxide-semiconductor (I-MOS) devices to circuit design

In this paper, the applicability of impact-ionization metal–oxide-semiconductor (I-MOS) devices has been discussed to some circuits such as static inverters, static NAND gates, static NOR gates, and 6T-SRAM cells. Based on detailed circuit analysis, some critical issues are overcome: cascadability, power consumption, series connection, and unidirectional output current. Complementary I-MOS (CI-MOS) inverters show higher noise margin and lower crowbar current than CMOS ones, which leads to the reduction of supply voltage and short-circuit power dissipation, respectively. In the case of static NAND and NOR gates, the CI-MOS also shows improved noise margin. Finally, CI-MOS 6T-SRAM cells show 22.6% improvement in SNM without much penalty in cell area compared with CMOS ones.

Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi- Vt CMOS application

Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low- V t CMOS FinFETs representing on-current enhancement and high- V t CMOS FinFETs reducing stand-by power dramatically, namely multi- V t CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with a low- V t configuration is demonstrated with excellent noise margins at a reduced supply voltage.

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 mum RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ) and the tuning-range figure of merit (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) are optimal at 12.79 dB/mW and 2.6 mW <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , respectively. The chip area is 0.89times0.89 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion

Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90nm CMOS technology. A 2Vpp input voltage range and 50µW power consumption were achieved by the measurements with a 0.5V supply. High accuracy of 62dB SNR was obtained at signal bandwidth of 120kHz.

Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS

This successive approximation register ADC uses time-interleaving to gain the energy advantage of slower circuits (reduced supply voltage and improved bias points) without sacrificing high speed operation. The drawbacks of interleaving are addressed through architectural solutions. Channel redundancy counteracts the severe yield loss that parallel circuits experience due to local variation. Clock partitioning restricts the distribution of the precise, high-speed sampling clock to three centrally located sampling networks. Only a low frequency clock is distributed across the majority of die area. The skew-resistant global top-plate sampling network is extended to allow overlapped sampling windows without introducing extra sources of crosstalk. The 36 -way interleaved 5-bit ADC operates with a core voltage of 800 mV and consumes 1.20 mW total power at 250 MS/s. At Nyquist, the SNDR is 28.4 dB. The 6 redundant channels (17% overhead) increase the yield of the 24 measured chips from 42% to 88%.

Gain-Enhancement Techniques for CMOS Folded Cascode LNAs at Low-Voltage Operations

In this paper, gain-enhancement techniques suitable for folded cascode low-noise amplifiers (LNAs) at low-voltage operations are presented. By employing a forward bias and a capacitive divider at the body of the MOSFETs, the LNA circuit can operate at a reduced supply voltage while maintaining an enhanced gain due to suppression of the negative impact of the body transconductance. In addition, G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosting stage is introduced to further increase the LNA gain at the cost of circuit linearity. Using a standard 0.18-mum CMOS process, two folded cascode LNAs are demonstrated at the 5-GHz band based on the proposed topologies. Consuming a dc power of 1.08 mW from a 0.6-V supply voltage, the LNA with the forward-body-bias technique demonstrates a gain of 10.0 dB and a noise figure of 3.37 dB. The measured P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1d</sub> B and IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> are -18 and -8.6 dBm, respectively. For the LNA with G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosting feedback, a remarkable gain of 14.1 dB gain is achieved with a dc power of 1.68 mW.

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

One of the most effective techniques to reduce a processor’s power consumption is to reduce supply voltage. However, reducing voltage in the context of manufacturing-induced parameter variations cancause many types of memory circuits to fail. As a result, voltage scaling is limited by a minimum voltage, often called Vccmin, beyond which circuits may not operate reliably. Large memory structures (e.g., caches) typically set Vccmin for the whole processor. In this paper, we propose two architectural techniques that enable microprocessor caches (L1and L2), to operate at low voltages despite very high memory cell failure rates. The Word-disable scheme combines two consecutive cache lines, to form a single cache line where only non-failing words are used. The Bit-fix scheme uses a quarter of the ways in a cache set to store positions and fix bits for failing bits in other ways of the set. During high voltage operation, both schemes allow use of the entire cache. During low voltage operation, they sacrifice cache capacity by 50% and 25%, respectively, to reduce Vccmin below 500mV. Compared to current designs with a Vccmin of 825mV, our schemes enable a 40% voltage reduction, which reduces power by 85% and energy per instruction (EPI) by 53%

Modeling and Optimization for Soft-Error Reliability of Sequential Circuits

Due to reduction in device feature size and supply voltage, the sensitivity to radiation-induced transient faults of digital systems dramatically increases. In this paper, we present two approaches to evaluating the susceptibility of sequential circuits to soft errors. The first approach uses the Markov chain theory but can only provide steady-state behavior information. The second approach uses symbolic modeling based on binary decision diagrams/algebraic decision diagrams and circuit unrolling. The soft-error rate (SER) evaluation using this approach is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4% average error and up to 11 000x faster when compared to HSPICE detailed circuit simulation. The framework can be used for selective gate sizing targeting radiation hardening, leading up to 80% SER reduction when applied to a subset of ISCAS'89 benchmarks.

Investigation of Thermal Noise in UTB GOI and SOI Devices

The thermal-noise performances of ultrathin-body silicon-on-insulator (SOI) and germanium-on-insulator (GOI) devices are investigated and compared through simulation in this paper. The figures-of-merit for noise characteristics are considered in terms of the minimum of noise figure (NFmin)and equivalent noise resistance (Rn). GOI devices exhibit better noise performance over SOI counterparts. The reduction in the supply voltage brings more distinct improvements of the noise performance of GOI devices. The dependence of noise parameters on the film thickness and spacer length is also analyzed. The results demonstrate that GOI devices are more suitable for RF and low-noise applications.

CMOS Transconductors With Continuous Tuning Using FGMOS Balanced Output Current Scaling

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A technique to achieve highly linear scaling of differential currents in CMOS technology is presented. It is based on operation in weak or moderate inversion, and features performance improvements over previous proposals aimed to the same goal, like reduced supply voltage requirements, increased power efficiency, and avoidance of bulk effect. As an example, this technique is applied to attain continuous tuning for two novel voltage-to-current converters, achieving highly linear programmable transconductance over a rail-to-rail input range. Both implementations fabricated in a 0.5-<formula formulatype="inline"> <tex>$\mu{\hbox {m}}$</tex></formula> CMOS technology using a dual supply of <formula formulatype="inline"><tex>$\pm$</tex></formula>1.5 V achieve a THD of <formula formulatype="inline"><tex>$-$</tex></formula>60 dB with differential input swings of 6 <formula formulatype="inline"><tex>${\rm V}_{\rm pp}$</tex></formula> (i.e., twice the supply voltage). The area and power consumption are 0.12 <formula formulatype="inline"><tex>${\hbox {mm}}^{2}$</tex> </formula> and 2.6 mW for the first implementation and 0.11 <formula formulatype="inline"> <tex>${\hbox {mm}}^{2}$</tex></formula> and 2.2 mW for the second one, respectively. </para>

Active load for differential amplifier with high output impedance and reduced supply voltage

An active load which uses positive feedback to achieve an impedance transformation is introduced. The use of this circuit as an active load for a differential amplifier is explored, and it is illustrated with a case study that the output impedance and consequently the voltage gain are improved when this circuit is used.

On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance

This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the needed cache line. This achieves better leakage savings than the best prior policies while avoiding the performance overheads of those policies, without needing an extra prediction structure. The proposed policy reduces leakage energy by 92.7 percent with only 0.08 percent performance overhead on average. The branch-prediction-based approach requires an extra pipeline stage for wake up, which adds to the branch misprediction penalty. Fortunately, this cost is mitigated because the extra wake-up stage is overlapped with misprediction recovery. This paper assumes the superdrowsy leakage control technique using reduced supply voltage because it is well suited to the instruction cache's criticality. However, the proposed policy can be also applied to other leakage-saving circuit techniques.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation

Design considerations for robustness with respect to variations and low-power operations typically impose contradictory design requirements. Low-power design techniques such as voltage scaling, dual- , etc., can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variation-tolerant circuit design called critical path isolation for timing adaptiveness (CRISTA), which allows aggressive voltage scaling. The principal idea includes the following: 1) isolate and predict the set of possible paths that may become critical under process variations; 2) ensure that they are activated rarely; and 3) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits with Berkeley-predictive-technology-model [BPTM 70 nm: Berkeley predictive technology model] 70-nm devices that show an average of 60% improvement in power with small overhead in performance and 18% overhead in die area compared to conventional design. We also present two applications of the proposed methodology that include the following: 1) pipeline design for low power and 2) temperature-adaptive circuit design.

Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement

High power consumption not only leads to short battery life for hand-held devices but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer grain power and performance tradeoff. In this paper, we propose a methodology on top of a set of algorithms to exploit nontrivial voltage island boundaries for optimal power versus design-cost tradeoff under performance requirement. Our algorithms are efficient, robust, and error-bounded and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a tenfold improvement of our method over current logical-boundary-based industry approach.

Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures

In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-mum CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP3 of -8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 muW, respectively.

Design of a PLL with improved locking range and its biomedical applications

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.

Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0,18-μm CMOS was measured at a 0.6-V supply, and achieved 89-nV/√Hz input referred noise (at 100Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-μW power dissipation at 1-V power supply.