Reduction Of Parasitic Capacitance Research Articles

20 GHz dynamic frequency divider with GaAs advanced SAINT and air-bridge technology

A GaAs BFL dynamic binary frequency divider is designed and fabricated using advanced SAINT with asymmetric n+-layers and air-bridge technology. Operation above 20 GHz is achieved due to advanced SAINT FETs with 0.3 μm gate length and the reduction of parasitic capacitances between interlayer lines.

GaAs Ultra-High-Frequency Dividers with Advanced Saint FET's

The circuit design, fabrication, and performance of ultra-high-frequency dividers with buffer FET logic (BFL) circuits are described. Using air-bridge technology and a new, self-aligned-gate, GaAs FET process, called advanced SAINT, which avoids excess gate metal overlap on the dielectric film, 10.6-GHz operation at 258 mW is achieved. This performance is made possible by a reduction of gate and interconnection parasitic capacitance. Furthermore, the possibility of operation above 20 GHz for GaAs MESFET frequency dividers is predicted on the basis of circuit optimization and FET improvements including parasitic capacitance reduction and transconductance enhancement.

GaAs ultra-high-frequency dividers with advanced SAINT FET's

The circuit design, fabrication, and performance of ultra-high-frequency dividers with buffer FET logic (BFL) circuits are described. Using air-bridge technology and a new, self-aligned-gate, GaAs FET process, called advanced SAINT, which avoids excess gate metal overlap on the dielectric film, 10.6-GHz operation at 258 mW is achieved. This performance is made possible by a reduction of gate and interconnection parasitic capacitance. Furthermore, the possibility of operation above 20 GHz for GaAs MESFET frequency dividers is predicted on the basis of circuit optimization and FET improvements including parasitic capacitance reduction and transconductance enhancement.

Above 10 GHz frequency dividers with GaAs advanced saint and air-bridge technology

GaAs advanced SAINT without excess gate metal overlap on the dielectric film and air-bridge technology are applied to dual-clocked BFL M/S binary frequency dividers. Operation above 10 GHz is achieved owing to reduction of gate parasitic capacitances and parasitic capacitances between interlayer lines.

Lattice Imaging of Heteroepitaxial Silicon on Sapphire

The silicon-on-sapphire technology has produced electronic devices with high switching speeds and low power consumption. These features are mainly due to the insulating nature of the substrate and the consequent reduction in parasitic capacitances. TEM observations of the crystalline structure of the silicon layer reveal the presence of large densities of twins and stacking faults, which are thought to have an adverse effect on the overall electrical characteristics of the devices and it is, therefore, desirable to understand their nature and origin.In this work the lattice structure of the silicon-sapphire junction has been imaged by high resolution TEM. The silicon layer was deposited at 960°C by chemical vapor deposition of silane in H2, at a rate of 1.4 μm/min on a (1102) sapphire substrate surface. The silicon was grown with its [001] direction perpendicular to the substrate plane to a thickness of 0.65 μm. Specimens were prepared in cross section with argon-ion bombardment as the final thinning step. TEM observations were performed with a Philips EM400 microscope equipped with a high resolution stage (spherical aberration coefficient of 1.1 mm) and a LaB6 filament, at an operating voltage of 120 kV.

Abstract: Recent advances in ion implantation

The progress in solid state technology is largely determined by our ability to control and modify certain materials parameters in a well defined manner. Semiconductors are a typical example, where minute traces of impurities in the order of parts per million and less will influence the electrical properties markedly.The concept of introducing such dopants into semiconductors by means of high energetic particles was discussed many years ago. In 1954, Shockley1 submitted a patent describing the ’’Forming of Semiconductor Devices by Ionic Bombardment.’’ As the semiconductor technology matured, developing shallower and shallower device structures, the control aspect became vitally important. And it is precisely in the field of control that ion implantation offers major advantages over standard diffusion technologies, e.g.,(a) Accurate control of the total amount of impurity transferred to the wafer by measurement of the accumulated charge during implantations.(b) A high degree of areal uniformity across the w...

New techniques for reduction of parasitic resistance and capacitance in integrated circuits : A. F. McKelvey, C. G. Thornton and G. L. Schnable, Proc. IEEE Symposium on “Molecular Concepts in Microelectronics”, St. Louis, May 24, 25, 26 (1965), p. 4D-1

New techniques for reduction of parasitic resistance and capacitance in integrated circuits : A. F. McKelvey, C. G. Thornton and G. L. Schnable, Proc. IEEE Symposium on “Molecular Concepts in Microelectronics”, St. Louis, May 24, 25, 26 (1965), p. 4D-1