Leakage Current Reduction Research Articles

Exploring the Potential of Tunnel Field-Effect Transistors in Biomedical Devices: A Comprehensive Survey

Implantable medical devices have revolutionized healthcare by providing continuous monitoring and therapeutic interventions within the human body. The overall performance of these devices is heavily dependent on the effectiveness and efficiency of integrated electronic components, such as transistors. This survey explores the growing utilization of Tunnel Field-Effect Transistors (TFETs) in implantable devices, shedding light on their advantages and challenges in this specific application domain. TFETs, characterized by their unique tunnelling mechanism, offer several advantages that make them well suited for implantable devices. Their low-power consumption, reduced leakage current, and improved subthreshold swing make them ideal for energy-efficient, long-lasting operation within the constrained power budgets of implantable devices. Furthermore, TFETs exhibit excellent performance at low supply voltages, ensuring minimal tissue damage and heat generation. This survey also addresses the challenges associated with TFETs in implantable devices, including fabrication complexities, variability, and compatibility with existing technologies. It highlights recent advancements in TFET technology that address these concerns, such as improved material choices and manufacturing techniques. As technology continues to advance, TFETs are poised to play a pivotal role in improving the overall efficiency and reliability of life-saving technologies and medical devices. Overall, this survey provides valuable insights into the current state and future prospects of TFETs in implantable devices, guiding researchers and engineers in harnessing their potential for the benefit of healthcare and patient well-being.

The Impact of Gate Annealing on Leakage Current and Radio Frequency Efficiency in AlGaN/GaN High-Electron-Mobility Transistors

Gallium Nitride (GaN) high-electron mobility transistors (HEMTs) are highly promising for high-frequency and high-power applications due to their superior properties, such as a wide energy bandgap and high carrier density. The performance of GaN HEMTs is significantly influenced by the interfacial states of the AlGaN barrier, and gate annealing has emerged as a key process for reducing leakage currents and enhancing DC/RF characteristics. This research investigates the impact of gate annealing on AlGaN/GaN HEMTs, focusing on two main aspects: leakage current reduction and improvements in DC and RF efficiency. Through comprehensive electrical analysis, including DC and RF measurements, the effects of gate annealing were experimentally evaluated. The results show a significant reduction in gate leakage current and noticeable improvements in DC/RF performance for the devices that underwent gate annealing. The study confirms that the annealing process can effectively enhance device performance by modifying the material properties at the gate interface.

Optimized substrate temperature for high-quality CdZnTe epitaxial film in X-ray flat panel detectors

Cadmium zinc telluride (CdZnTe or CZT) materials, favored for their physical superiority in optoelectronic applications, can be efficiently produced as large-area epitaxial film via close space sublimation (CSS), enhancing potential in flat-panel detector imaging. However, the application of CdZnTe epitaxial film in medical imaging equipment is limited by their lower resistivity, prolonged response times, and diminished sensitivity. By elevating the substrate temperature, we enhanced the number and depth of reverse sublimation pits on the surface of the CdZnTe epitaxial film, established an approximately 100 nm Zn-rich layer, broadened the bandwidth, and minimized electrode injection. Additionally, we observed an aggregation of dislocations at the edges of the reverse sublimation pits, which promoted surface recombination and reduced leakage current. These modifications significantly increased the film's resistivity to 1011 Ω cm. Further, they notably decreased the rise and drop times to 2 m s and 4 m s, respectively. Integrated with thin-film transistors (TFTs), the optimized CdZnTe epitaxial film now distinctly differentiate between air, plastics, and metals under X-ray examination. This improved performance of X-ray flat panel detectors (FPDs) based on CdZnTe epitaxial film is promising for the development of next-generation X-ray detection systems.

Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance

This study focuses on the design and analysis of Junctionless (JL) NSFETs, with an emphasis on the influence of spacer materials and temperature variations. A different number of materials such as Air, SiO2, Si3N4, HfO2, and TiO2 are examined for sidewall spacer compatibility in the JL-NSFET. The same materials are used for dual material spacers with combinations of: Air+HfO2, Air+TiO2, SiO2+HfO2, and SiO2+TiO2. The investigations revealed that the usage of TiO2 material gives better digital and analog performance with reduced leakage currents and subthreshold swing (SS), higher on/off ratio, voltage gain of ∼79.7 dB. Exploring the dual-k spacers produced better analog performance, gate control and reduced leakages for SiO2+TiO2 owing to the usage of higher dielectric material towards the gate. Further, the reduction of temperature from 400 K to 250 K for all the single-k and dual-k spacer materials revealed that the designed JL-NSFET is a suitable candidate at lower temperatures to improve the digital and analog performance whereas not recommended for RF performance improvement. Moreover, the SiO2+HfO2 spacer-based CMOS inverter is noticed to have better gain (∼15 V/V), noise margin, and lower delays (∼5.1 ps) when compared to TiO2 spacer-based complementary metal oxide semiconductor inverter making it suitable for digital IC applications.

Growth of single crystalline GeSn alloy epilayer on Gd2O3/Si (111) engineered insulating substrate using RF sputtering and solid phase epitaxy

The article showcases a low-cost, low-temperature deposition andHVMtechnique to develop single crystalline GeSn alloy epilayers on Gd2O3/Si (111) substrate. First, GeSn alloy amorphous layer is deposited on the insulating substrates using an Radio Frequency (RF) sputtering apparatus. Subsequently, an inductively coupled plasma-assisted chemical vapor deposition (ICP-CVD) process is used to deposit a SiO2 capping layer to protect against Sn out-diffusion during heat treatment. The samples are then subjected to solid phase epitaxy (SPE) at 450 °C, 550 °C, and 650 °C. Sample processed for SPE at 450 °C has weak crystallinity and only shows Type-A stacking. Those processed for SPE at 550 °C and 650 °C, on the other hand, have revealed formation of the single-crystalline GeSn alloy epilayer with Type-A and Type-B stacking. However, SPE at 650 °C revealed tin out-diffusion and segregation effects. This work is significant for enabling the preparation of high-Sn-content GeSn alloy epilayers on insulating Gd2O3/Si (111) substrates, as it requires the initial deposition of a GeSn amorphous alloy epilayer using RF sputtering. This advancement promises benefits which includes advantages such as lower operating voltage, reduced leakage current, and minimized parasitic and short-channel effects, making it ideal for advancing RF technology.

Enhanced Threshold Voltage and Improved Subthreshold Swing Using NiOX/ITO Reverse Bias Gated Diamond pMOS

An increase in the device performance of diamond‐based p‐type metal–oxide–semiconductor (pMOS) transistors using a combination of p‐type nickel oxide and n‐type indium tin oxide (NiOX/ITO) reverse bias diode as the gate dielectric is reported. Negative threshold voltage pMOS transistors are desirable for digital circuits and power applications for fail‐safe operation. A Schottky gate‐based conventional diamond pMOS transistor suffers from many limitations, including a positive threshold voltage (VT). Herein, it is experimentally demonstrated that NiOX/ITO gate dielectric with Al gate contact circumvents many critical limitations, providing a negative threshold voltage of −1.2 V, improved subthreshold slope of 145 mV dec−1, current ON/OFF ratio >107, and peak gate leakage current reduction >103. An Al/NiOX‐based control gate structure shifts the VTH negative with improvements in crucial device performances. Adding a reverse bias junction through the Al/ITO/NiOX heterointerface with the Al metal gate further improves performance. The measured device characteristics are explained in a common framework of energy band diagram for all the devices.

Performance Enhancement and Mechanism Analysis of IGZO Thin-Film Transistors Utilizing Interdigital Structure

This study investigates the issue of leakage current reduction in oxide semiconductor thin-film transistors (TFTs) with interdigital structures. Electrical measurements clearly demonstrate that the leakage current of interdigitated IGZO devices decreases as the on/off ratio increases. To explore the reasons behind the reduction in leakage current, we conducted two-dimensional device simulations. The results confirm that the use of interdigital structures can influence the electric field distribution within the device channel, introducing shielding electric fields. As the number of interlayer structures between the source and drain increases, the shielding electric fields proportionally increase. Additionally, interdigitated IGZO devices exhibit a large on/off ratio exceeding 2.7×1010, an ultra-low leakage current of less than 3×10-16 A/μm, and a high saturation mobility of 9.4 cm2/Vs. These findings provide valuable insights for designing low-power, high-performance devices based on IGZO.

Systematic investigation of the influence of magnetic and non-magnetic ion substitutions in BiFeO3 under similar internal chemical pressure

Polycrystalline Bi1-xRxFeO3 (RHo and Y, x = 0.00, 0.05 and 0.10) compounds were prepared to perform a systematic investigation of the role of chemical nature and effect of internal chemical pressure on the structural, microstructural, magnetic, electric, ferroelectric and optical properties of the compounds. Structural analysis revealed that lattice distortions observed in Ho and Y-substituted compounds were not the same. The lattice parameters were larger in the case of the Y-substitution compared to the Ho-substituted counterpart. Scanning electron micrographs confirmed the formation of dense, well-connected grains exhibiting a reduction in size with increasing substitution. The magnetic properties of BiFeO3 were enhanced through the suppression of the spin structure with the substitution. The substitution of magnetic (Ho3+) ions led to an improvement in remanent magnetization and coercive field, whereas the substitution of non-magnetic (Y3+) ions resulted in enhanced maximum magnetization with negligible coercive field at room temperature. The ferroelectric measurements evidenced that both remanent polarization and coercive fields improved in substituted compounds, attributed to a decrease in charge carriers. Furthermore, the Y3+ ion substitution positively influenced ferroelectric properties by reducing leakage currents compared to the Ho3+ ion substitution. The optical absorption measurements indicated a decrease in the energy band gap of BiFeO3 with substitution, implying alterations in the material's optical characteristics. The ac conductivity studies demonstrated a discernible reduction in the conductivity of the substituted compounds. Specifically, Ho-substitution exhibited a more pronounced magnitude in the decline in conductivity relative to Y-substitution. This outcome signifies the potential efficacy of Ho-substitution in exerting control over the insulating characteristics of the compounds.

Strain evolution from the ferroelectric to the relaxor state in (0.67 - x)BiFeO3-0.33BaTiO3-xBi(Mg0.5Zr0.5)O3 lead-free ceramics.

The BiFeO3-BaTiO3 solid solution exhibits enhanced electric properties due to its modified phase structure with relaxor characteristics and reduced leakage current. Despite these advancements, the underlying mechanism behind the phase transition from a ferroelectric to a relaxor state in BF-BT ceramics remains largely unexplored. Here, the evolution of strain in (0.67 - x)BiFeO3-0.33BaTiO3-xBi(Mg0.5Zr0.5)O3 ceramics is investigated, with a focus on the strain transition from a ferroelectric to a relaxor phase. A strengthening of relaxor behavior is observed in the modified rhombohedral (R) and pseudocubic (PC) phase structure, resulting in optimal strain (Suni = 0.25%, Spos = 0.24%) at x = 0.04. The enhanced strain is attributed to the promotion of domain switching and the presence of strong random fields, with polar nanoregions integrating into a long-range ordered matrix. Furthermore, a gradual increase in strain with rising temperature is noted, driven by increased polarization and the expansion of ferroelectric domains. This study underscores the critical role of structural modifications in augmenting the electric response of BF-BT ceramics, thereby advancing the development of lead-free piezoelectric materials.

A Self‐Assembling Molecule for Improving the Mobility in PEDOT:PSS Hole Transport Layer for Efficient Perovskite Light‐Emitting Diodes

AbstractPoly(3,4‐ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS), the most widely used hole injection layer (HIL) for perovskite light‐emitting diodes (PeLEDs), has a large hole injection energy barrier and easy charge separation at PEDOT:PSS/perovskite layer. Here, a self‐assembling molecule (SAM) called (2‐(3,6‐dimethoxy‐9H‐carbazol‐9‐yl)ethyl) phosphonic acid (MeO‐2PACz) is introduced as an interlayer between PEDOT:PSS and perovskite to overcome the limitations of PEDOT:PSS HIL. The MeO‐2PACz interlayer facilitated hole injection due to the reduced hole injection energy barrier and the improved hole mobility, enhanced photoluminescence (PL) due to the prevented charge transfer from perovskite into PEDOT:PSS, and reduced interface trap density due to the passivation of methoxy and carbazole group toward perovskite. As a result, PeLEDs with MeO‐2PACz interlayer has greatly enhanced maximum luminance (Lmax = 17,310 cd m−2) and reduced leakage current, resulting in higher maximum external quantum efficiency (EQEmax = 21.50%) compared to pristine Control device (EQEmax of 4.82%).

Leakage current in GaN-on-GaN vertical GaN SBDs grown by HVPE on native GaN substrates

This study investigates leakage mechanisms in vertical GaN-on-GaN Schottky barrier diodes (SBDs) and demonstrates effective mitigation strategies. The fabricated devices exhibit low reverse leakage current (1 × 10−5 A/cm2 at −200 V) and a high Ion/Ioff ratio (∼1010), surpassing the performance of GaN SBDs on foreign substrates. We elucidate dominant leakage mechanisms—thermionic emission, Poole–Frenkel emission, and variable-range hopping—and their evolution with temperature and bias. Optimized fabrication processes, including defect etching and a novel dual-layer passivation technique, achieve over a 1000-fold reduction in leakage current.

A new single-source, single-phase, 9-L 4-B switched capacitor-based multilevel inverter

ABSTRACT All types of non-conventional energy sources (NCES) produce low voltage, but offer it to be converted into usable and essential form. Switched capacitor multilevel inverter (SC-MLIs) has played a vital role in extracting power from NCES to fulfill the requirements of today’s need. Researchers have shown a great interest in extracting this power which comes from solar PV, wind, fuel cells and other miniature sources which is often not significant at all. This research offers a topology that is very simple and easy to implement. The authors also demonstrate a novel SC-MLI with a single ground and four voltage boosting capabilities. This paper analyzes and reviews the suggested inverter can create nine levels along with four times the voltage from a single dc source. Three self-balanced switched capacitors in association with a pair of five switches and single diode are used to offer quadruple boosting. A level-shifted pulse width modulation technique helps to generate the output voltage. The execution of the SC-MLI and the capacitor architecture for the suggested topology are fully investigated. The availability of common neutral is advantageous in reducing leakage current, especially in green energy utilization. In the context of voltage gain, the number of components employed, and the presence of common neutral, the designed inverter is contrasted to several other previously revealed inverters.

A novel 4H–SiC thermal neutron detector based on a metal-oxide-semiconductor structure

Energy resolution and leakage current are two key parameters for semiconductor neutron detectors. Metal-Oxide-Semiconductor (MOS) detectors introduce an additional oxide layer compared to Schottky Barrier Diodes (SBDs) detectors in order to reduce leakage current. However, this also leads to a degradation in energy resolution due to the introduction of an additional dead layer. Therefore, optimizing the thickness of the oxide layer is important for MOS detectors. In this study, a 4H–SiC-based MOS thermal neutron detector was designed with comprehensive consideration of the oxide layer. Subsequently, a prototype of the detector was fabricated and tested. The prototype of the MOS detector achieved an nA-level leakage current under a reverse bias of −200 V. Additionally, it demonstrated good energy resolution performance in a moderated D-T neutron source test. The MOS detector was able to clearly distinguish between the two reaction channels of 10B converter events, which is consistent with the theoretical branching ratio. This work highlights the potential application of 4H–SiC-based MOS detectors for thermal neutron detection.

Phase transition kinetics and sublayer optimization of HfO2/ZrO2 superlattice ferroelectric thin films

The sublayer thickness of superlattices, as a key factor affecting lattice integrity, interface defects, and strain, deserves in-depth studies about its impact on improving ferroelectric properties. This study described and analyzed the performance of HfO2/ZrO2 superlattices with various sublayer thicknesses. It can be concluded that the structure of the thicker layers will guide the trend of the phase composition of the entire device: when ZrO2 layers are thicker, the superlattices will exhibit antiferroelectricity due to the higher content of the tetragonal phase (t-phase); when HfO2 layers become thicker, the fraction of the monoclinic phase (m-phase) will increase, leading to a decrease in ferroelectricity and an increase in leakage current. In this way, the device with a 1:1 HfO2/ZrO2 thickness ratio was optimized to have the largest remanent polarization and the lowest leakage current. Maintaining the same thickness ratio of the HfO2/ZrO2 superlattices, it was found that HfO2/ZrO2 superlattices with thinner sublayers exhibited a larger remanent polarization (Pr) value due to increased interlayer distortion. On the contrary, the thicker sublayers reduced leakage current, which was beneficial for improving the device lifespan.

Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application

Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.

Solution to SRAM static power consumption with MTCMOS

The rapid growth of mobile devices has led to an increasing demand for battery life and energy efficiency in recent years, the reduction of circuit power consumption has become extremely crucial. SRAM has become an indispensable component of modern System-on-Chip (SoC) designs, and reducing its power consumption holds significant importance in minimizing overall chip power consumption. On the other hand, as manufacturing processes advance, static power consumption resulting from leakage currents has gradually emerged as a primary source of power consumption. This paper analyzes the power composition of SRAM, provides a detailed explanation of the principles and influencing factors of MTCMOS design technology, and conducts modeling analysis on 6T SRAM based on MTCMOS. In the modeling analysis, we compare the leakage current and static power reduction effects of 6T SRAM using four different process technologies: 28nm, 40nm, 65nm, and 90nm. From the data, it can be observed that MTCMOS has a notable effect in reducing leakage current for 6T SRAM across various process technologies. Comparing 6T SRAM of different process technologies, we can roughly see that the power reduction effect reaches a peak and gradually decreases. However, due to the lack of more advanced process libraries, we cannot further validate whether this inference is accurate.

Role of oxygen vacancy in controlling the resistive switching mechanism for the development of conducting filaments in response of homo and hetero electrodes: Using DFT approach

In the realm of progression of internet of things, artificial intelligence and cloud services, nonvolatile memory devices such as, resistive random access memory (RRAM) emulated the vision of building internet of everything. In this study, robustness of homo- (Ag–Ag, and Pt–Pt), and hetero- (Ag–Pt) top, and bottom electrodes material without and with incorporated oxygen vacancies (Vos) in Sr4Ti4O12 RS layer were investigated. Presence of conductivity in the absence of external electric field proves the presence of nonvolatile memory behavior. Observed RS behavior (in the range of a few Angstroms) may be used to resolve the scalability issue of the proposed RRAM device system. At the same time, oxygen vacancies (Vos) introduced additional functionalities like: additional reduction sites, and reduction of leakage current by quantizing the conduction within RS material. Diffusion barrier elucidated the diffusion mechanism of oxygen vacancies in the considered heterostructure to understand the energy state and the type of RS conduction mechanism. Potential energy line ups, formation energy and electronic properties identified the Vos as principal sites for reduction of Ag atoms by forming metal oxide (Ag-Vos) complex. It is predicted that ReSET, and hence high resistance state (HRS) is harder to achieve with homo-electrodes. The findings of this study provides the effective solution to scalability, stability, and low power consumption in the realm of Pt–Sr4Ti4O12–Ag (with 2Vos mediated in RS layer) based RRAM devices.

Stepped ohmic structure of AlGaN/GaN HEMT with lower off-state leakage current

Abstract Utilizing the TCAD-ATLAS platform, we performed accurate fitting of the electrical characteristics of GaN HEMT devices, achieving a fitting error of less than 5%. Building upon this parameter fitting, we introduced a stepped ohmic structure and compared it with the conventional rectangular structure. The findings highlight the significant impact of the ohmic structure on the off-state drain leakage current of the device. Through the implementation of the stepped ohmic structure, a remarkable reduction in the off-state leakage current was achieved. Specifically, the off-state leakage current decreased by three orders of magnitude, declining from 10−5 mA/mm to 10−8 mA/mm. Importantly, this improvement in leakage current was accomplished without adversely affecting the device’s output characteristics. These results underscore the effectiveness of the stepped ohmic structure in enhancing the overall performance of GaN HEMT devices.

H/O edge passivated B/N co-doped armchair graphene nanoribbon field-effect transistors, based on first principles

This study employs the nonequilibrium Green’s function method in conjunction with density functional theory to fabricate and analyze a Graphene Nanoribbon Field-Effect Transistor (GNRFET). The co-doping of B and N creates built-in electric fields, thereby reducing leakage current. The results demonstrate effective control performance of planar gates, as evidenced by an increase in IDS with rising gate voltage. Furthermore, a negative differential conductance phenomenon is observed at bias voltages exceeding 0.7 V, exhibiting correlation with transmission spectra and energy band structures. To precisely illustrate the electron distribution within the doped scattering region, calculations involving transport paths, the molecular projection self-consistent Hamiltonian (MPSH), and the emission eigenvalues and eigenstates of the device are conducted. This research provides a reference for exploring and developing smaller and more energy-efficient AGNR field effect transistor designs and implementations. The principal objective of this paper is to investigate the potential applications of these smaller, more energy-efficient devices.

Suppressing leakage current and charge accumulation via perovskite interface morphology regulation for efficient light-emitting diodes

Charge carriers will recombine outside the emitting layer (EML) in non-ideal perovskite light-emitting diodes (PeLEDs), which can lead to parasitic loss and be detrimental to the performance of PeLEDs. Here, we have subtly utilized the property of perovskite nanocrystals (NCs) to design and optimize the homogeneity and optical property of EML, thereby suppressing the undesired carrier loss behavior in system. Photoluminescence (PL) spectra with transmission electron microscopy (TEM) images show that smaller and more homogeneous NCs in size are obtained by temperature-controlled (TC) method. Atomic force microscopy (AFM) images and temperature-dependent PL spectra show that EML with better optical property and uniformity is fabricated. The multiscale capacitance characterization shows that the device with modified EML exhibits significantly reduced leakage current, while the increased specific surface area between electron transport layer (ETL) and EML substantially reduces charge accumulation. Additionally, multiscale reactance, impedance and phase angle responses, reveal that the carrier oscillation behavior in the optimized device is suppressed compared to control group, leading to less energy loss. Consequently, the optimized devices exhibit lower leakage current and superior electroluminescent properties. The luminance is increased from 31650 cd/m2 to 72941 cd/m2, current efficiency (CE) is improved from 59.9 cd/A to 94.3 cd/A, and the external quantum efficiency (EQE) rises from 12.6 % to 19.7 %, corresponding to improvement of 230 %, 157 %, and 156 %, respectively. This research provides valuable insight into the impact of functional layer morphology on carrier dynamic behavior in PeLEDs.