Reduction In Gate Oxide Thickness Research Articles

P-SiGe nanosheet line tunnel field-effect transistors with ample exploitation of ferroelectric

This work illustrates the ample exploitation of ferroelectric through metal-ferroelectric options for nanosheet line tunnel field-effect transistor (NLTFET), for the first time. Here, SiGe and ferroelectric (HZO) are successfully employed to demonstrate the high performance p-NLTFET through simulations. Owing to this, the on-state current (I on = 122.3 μA μm−1) is enormously improved through the reduction of gate-oxide thickness even at low gate bias. In addition, the steep subthreshold swing is effectively minimized to 25.96 mV dec−1 by controlling the off-state current, gate-leakage and trap-assisted-tunneling. Overall, a 2-order boost on the I on is achieved, compared with planar ferroelectric TFETs.

Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology

In this work, we explore the gate oxide thickness influence on the Gate Induced Floating Body effect (GIFBE). This study was performed through two-dimensional numerical simulations and electrical measurements. The available devices are from 130nm and 65nm Silicon-On-Insulator (SOI) MOSFET technologies. The GIFBE and threshold voltage are evaluated as function of the gate oxide thickness reduction and an overlap tendency of the first and the second transconductance peaks is observed.

Roles of Gate-Oxide Thickness Reduction in Scaling Bulk and Thin-Body Tunnel Field-Effect Transistors

Tunnel field-effect transistor (TFET) has recently been considered as a promising candidate for low-power integrated circuits. In this paper, we present an adequate examination on the roles of gate-oxide thickness reduction in scaling bulk and thin-body TFETs. It is shown that the short-channel performance of TFETs has to be characterized by both the off-current and the subthreshold swing because their physical origins are completely different. The reduction of gate-oxide thickness plays an important role in maintaining low subthreshold swing whereas it shows a less role in suppressing off-state leakage in short-channel TFETs with bulk and thin-body structures. When scaling the gate-oxide thickness, the short-channel effect is suppressed more effectively in thin-body TFETs than in bulk devices. Clearly understanding the roles of scaling gate-oxide thickness is necessary in designing advanced scaled TFET devices.

Effect of Gate Oxide Thickness on Negative Bias Temperature Instability in p-Mosfet with Sion Gate Dielectrics

The major reliability issue of metal-oxide-semiconductor field-effect-transistor (MOSFET) had been mainly hot carrier injection (HCI) until the late 1990s. However, negative bias temperature instability (NBTI) has been focused on since late 1990s until now because both aggressive scaling-down of gate oxide thickness and nitrogen incorporation into gate oxide, which mitigate HCI, enhance NBTI severely [1-2]. Although the phenomenon of bias temperature instability (BTI) has been known for several decades, there is still no clear explanation regarding the roles of gate oxide thickness on NBTI degradation of p-MOSFETs. For example, N. Kimizuka et al. reported that NBTI lifetime in p-MOSFET with thin gate oxide is larger than that with thick gate oxide under equivalent oxide field stress in the range of 2.0 ~ 4.0 nm oxide thickness [3]. On the contrary, S. Mahapatra et al. reported that BTI could be enhanced in p-MOSFET with thinner gate oxide due to high diffusivity of H2 in gate poly [4]. Meanwhile, G. Pobegen et al. reported that NBTI were all the same in p-MOSFETs with gate oxide thickness of 5.6, 13.9 and 29.1 nm [5]. In this work, we tried to resolve conflicting experimental results reported in the literature: Since the reduction of gate oxide thickness will enhance electric field across gate oxide, the application of thinner gate oxide will deteriorate NBTI degradation such like threshold voltage shift (ΔVt) caused by charge generation. However, it also increases oxide capacitance, reducing the effect of generated positive charge which is one of the main sources for NBTI degradation. We fabricated p-MOSFET devices with SiON gate oxide and p+ poly-silicon gate stack in the commercial graded production line through conventional DRAM full processes. We evaluated p-MOSFETs with two different thicknesses of gate oxide: One is p-MOSFETs with thin gate oxide of 3.36 nm (‘thin PMOS’ hereafter), and the other is p-MOSFETs with gate oxide of 7.27 nm (‘thick PMOS’ hereafter). We evaluated NBTI degradation electrically by measuring the threshold voltage (Vt) before and after NBT stress for 1,000 seconds at 125 °C with Agilent 4156C. By means of stressing for 1,000 seconds without a break and by measuring just after stress, we could minimize undesirable variations caused by recovery. Data shown in Fig. 1(a) represent ΔVt caused by NBT stress of various gate voltages. In Fig. 1(a), the slope of ΔVt for thin PMOS devices is steeper than that of thick PMOS. However, if we redraw the same data of ΔVt as a function of oxide electric field (Eox), then we have the same ΔVtslope for both thin and thick PMOS devices regardless of gate oxide thickness, as shown in Fig. 1(b). NBTI has been known to be exponentially increased with oxide electric field [6], which expressed empirically as Eq. (1). Our NBTI data of both thin and thick PMOS have the identical B value of 0.69 cm/MV. Also, NBTI is generally known to be caused by both interface trap and positive oxide charge which were generated during the NBT stress [6]. The generated charges contribute to threshold voltage shift via Eq. (2). Therefore, the total increased charge density (ΔNtotal) can be written as Eq. (3). By using Eq. (3), the correlation between the increased trap density and the oxide field applied during the NBT stress test can be obtained from the data in Fig. 1(b), and the result is shown in Fig. 1(c), in which all data lay on the one straight line. This suggests that NBT stress with the equivalent oxide field causes the same amount of increased charges independent of gate oxide thickness. Therefore, Eq. (1) must be normalized by Coxto count this observation as Eq. (4). As shown in Fig. 2, it is remarkable that NBTI degradation becomes the minimum at the condition of Eq. (5). NBTI drops drastically down to the minimum point and then rises with the increase of gate oxide thickness, which accounts for the previous conflicting experimental results. In summary, we found that the total increased charge density of the devices subjected to NBT stress is same as long as the equivalent electric field is applied, regardless of gate oxide thickness. By modifying the empirical equation for ΔVt, we suggest that the optimal value of Tox can be selected for a given gate voltage and oxide field acceleration coefficient. This finding can be served as the new guideline on selecting gate voltage and gate oxide thickness to minimize the NBTI degradation both for process development and integrated circuit design. Figure 1

Dual Metal/High-kGate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

Dual Metal/High-k Gate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

Novel attributes in scaling issues of carbon nanotube field-effect transistors

For the first time, we present a scaling study of carbon nanotube field-effect transistors (CNTFETs) using a two-dimensional model. We investigate the scaling issues in device performance focusing on transconductance characteristics, output characteristics, average velocity, I on/ I off ratio, subthreshold swing and drain-induced barrier lowering (DIBL) with different gate oxide thicknesses and carbon nanotube (CNT) diameters. We concluded that the I on/ I off ratio increases with the gate oxide thickness reduction and increase in the CNT diameter and lead to a high on-state current. Furthermore, leakage current reduces with decrease in the gate oxide thickness, but it becomes higher in CNTFETs with larger CNT diameter. Also, our results show the output conductance, transconductance, voltage gain and average electron velocity at the top of the barrier improve in CNTFETs with thinner gate oxide and larger CNT diameter. In addition, the investigation of short channel effects shows that CNTFETs with thinner gate oxide offer lower DIBL and subthreshold swing, but in the CNTFETs with larger CNT diameter DIBL and subthreshold swing become worse.

The Impact of the Gate Oxide Thickness Reduction on the Gate Induced Floating Body Effect in SOI nMOSFETs

This work presents the influence of the gate oxide thickness (toxf) reduction on the gate induced floating body effects (GIFBE) in different Silicon On Insulator (SOI) technologies, through experimental results and two-dimensional numerical simulations. The occurrence of the floating body effect displacement and the threshold variation with toxf reduction are investigated. The continuous reduction of toxf suggests that the first and second transconductance peaks tend to overlap each other.

Optimization of Embedded Compact Nonvolatile Memories for Sub-100-nm CMOS Generations

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.

A Physically Based Analytical Model for the Threshold Voltage of Strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.

Impact of electron and hole inversion-layer capacitance on low voltage operation of scaled n- and p-MOSFET's

The influence of inversion-layer capacitance (C/sub inv/) on supply voltage (V/sub dd/) of n- and p-MOSFET's is quantitatively examined. The physical origin of the effect of C/sub inv/ on V/sub dd/ consists in the band bending of a Si substrate in the inversion condition due to C/sub inv/, which is not scaled with a reduction in gate oxide thickness. The amount and the impact of the band bending is accurately evaluated on a basis of one dimensional (1-D) self-consistent calculations including two-dimensional (2-D) subband structure of inversion-layer electrons and holes. It is demonstrated that additional band bending of a Si substrate due to C/sub inv/ becomes a dominant factor to limit the lowering of V/sub dd/ for CMOS with ultrathin gate oxides. The operation at V/sub dd/ lower than 0.6 V is quite difficult even with effective T/sub ox/ less than 1 nm.