Reduce Circuit Area Research Articles

Analog Approximate-FFT 8/16-Beam Algorithms, Architectures and CMOS Circuits for 5G Beamforming MIMO Transceivers

Emerging millimeter-wave (mmW) wireless systems require beamforming and multiple-input multiple-output (MIMO) approaches in order to mitigate path loss, obstructions, and attenuation of the communication channel. Sharp mmW beams are essential for this purpose and must support baseband bandwidths of at least 1 GHz to facilitate higher system capacity. This paper explores a baseband multi-beamforming method based on the spatial Fourier transform. Approximate computing techniques are used to propose a low-complexity fast algorithm with sparse factorizations that neatly map to integer $W/L$ ratios in CMOS current mirrors. The resulting approximate fast Fourier transform (FFT) can thus be efficiently realized using CMOS analog integrated circuits to generate multiple, parallel mmW beams in both transmit and receive modes. The paper proposes both 8- and 16-point approximate-FFT algorithms together with circuit theory and design information for 65-nm CMOS implementations. Post-layout simulations of the 8-point circuit in Cadence Spectre provide well-defined mmW beam shapes, a baseband bandwidth of 2.7 GHz, a power consumption of 70 mW, and a dynamic range >42.2 dB. Preliminary experimental results confirm the basic functionality of the 8-beam circuit. Schematic-level analysis of the 16-beam I/Q version show worst-case and average side lobe levels of −10.2 dB and −12.2 dB at 1 GHz bandwidth, and −9.1 dB and −11.3 dB at 1.5 GHz bandwidth. The proposed multi-beam architectures have the potential to reduce circuit area and power requirements while meeting the bandwidth requirements of emerging 5G baseband systems.

Folded Circuit Synthesis

The area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show how to modify the Boolean network describing a combinational logic to increase the opportunities for folding, without affecting its function. Experiments with benchmark circuits achieved an average reduction in circuit area of 18%.

Compact, wideband impedance tuner using a three‐line‐microstrip structure

A novel three-line-microstrip compact impedance tuner is presented. It is based on a multimodal structure wherein six variable capacitances, implemented with two parallel-connected varactors each, create multiple interactions among the three-line-microstrip modes in a reduced circuit area. Experimental results show better-than-70% coverage of the Smith chart in an 85% frequency bandwidth from 1.4 to 3.2 GHz.

Compact rectenna based on a fractal geometry with a high conversion energy efficiency per area

This work presents the design of a rectenna topology by using a compact microstrip patch antenna based on a fractal model and with the rectifier circuit integrated into the same physical structure. This configuration presents a very reduced circuit area, which makes the proposed rectenna circuit suitable for harvesting and wireless power transfer applications where the size is critical. The proposed compact rectenna, implemented on a low-cost FR-4 substrate, can harvest RF power from 2.45 GHz (ISM band) with a efficiency of ∼62% when the input power harvested by the rectenna is +2 dBm. The suggested rectenna has been manufactured and experimentally characterised, showing a good agreement with the expected simulated results.

Optimization of Constant Matrix Multiplication with Low Power and High Throughput

Constant matrix multiplication (CMM), i.e., the multiplication of a constant matrix with a vector, is a common operation in digital signal processing. It is a generalization of multiple constant multiplication (MCM) where a single variable is multiplied by a constant vector. Like MCM, CMM can be reduced to additions/subtractions and bit shifts. Finding a circuit with minimal number of add/subtract operations is known as the CMM problem. While this leads to a reduction in circuit area it may be less efficient for power consumption or throughput. It is well studied for the MCM problem that a) reducing the adder depth (AD) leads to a reduced power consumption and b) pipeline resources have to be considered during optimization to enhance throughput without wasting area. This paper addresses the optimization of CMM circuits which considers both adder depth and pipelining for the first time. For that, a heuristic is proposed which evaluates the most attractive graph topologies. It is shown that the proposed method requires 12.5% less adders with min. AD and 38.5% less pipelined operations. Synthesis results for recent FPGAs show that these reductions also translate to superior results in terms of delay and power consumption compared to the state-of-the-art.

Low Latency IDMA With Interleaved Domain Architecture for 5G Communications

Non-orthogonal multiple access (NOMA) is a promising candidate for the future fifth generation systems because of its ability to provide greater spectral efficiency. Interleave division multiple access (IDMA) is one of the NOMA techniques that can support multiple access for a large number of users in the same bandwidth. One of the problems in the hardware implementation of IDMA is its high latency due to iterative processing. In this paper, we propose a novel architecture for the IDMA receiver with low latency while maintaining low complexity. In the conventional architecture, the IDMA receiver sequentially handles deinterleaving, despreading, spreading, and interleaving for multi-user detection. The proposed architecture which we call interleaved domain multi-user detection can perform multi-user detection directly without deinterleaving the received frame in the interference canceller iteration resulting in the decrease of latency by almost half. We also describe the memory design which is able to implement the proposed architecture. The results show that due to the reduction of the latency by half, the throughput can be increased by twice compared with the conventional architecture. VLSI implementation results show that the proposed architecture has reduced circuit area and power consumption by 53% and 58%, respectively, compared with the conventional architecture with the same throughput condition.

Domain Wall Interconnections for NML

Nanomagnet logic (NML) is one of the most novel solutions studied as complementary technology to CMOS transistors. Information propagation involves only a change in spin orientation, no charge movement is present. Since the basic element is a nanomagnet, NML circuits have no stand-by power consumption and the ability to mix logic and memory in the same device. While CMOS is a multilayer technology, until now NML is confined to one single physical layer. The consequence is that circuit area grows exponentially due to interconnections overhead. In this paper, we present an innovative solution that drastically reduces the area wasted for interconnection wires relying on the properties of domain walls (DWs). We mix DWs and NML technologies in a unique DW logic (DWL) solution that exploits the advantages of both technologies. The proposed solution is technologically compatible with up-to-date fabrication processes. All the results here presented for the NML logic blocks and the DWs interconnections and their combination are obtained through rigorous micromagnetic simulations. Moreover, we implemented as a case study an high performance adder (Pentium 4 adder) and evaluated its features with increasing parallelism and compared with the simple NML implementation in order to explore the potential of DWL technology at circuit and architectural level. The reduction in circuit area corresponds to a notable reduction in both the latency and power consumption. The improvements in NML technology are shown by both the remarkable performance improvement and new possibilities offered by this novel solution.

High-Speed, Low-Power, and Error-Free Asynchronous Write Circuit for STT-MRAM and Logic

Benefiting from its simple switching scheme (only a bidirectional current source), high-speed and low-power spin-transfer torque (STT) has been regarded as one of the most promising switching mechanisms for a magnetic tunnel junction (MTJ)-based non-volatile memory and logic circuits. However, it suffers from a number of reliability issues like write error induced by its intrinsic stochasticity, process variation, and so on. In order to reduce the write error rate, the mainstream solution is to enlarge the write pulse duration at the expense of write energy dissipation. Some self-terminated write circuits have been proposed to avoid the wasted write energy. But the hardware cost of these write circuits is especially large. In this paper, a novel cost-efficient self-terminated write circuit is proposed using two simple built-in sensing circuits. The proposed write circuit is simulated with a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit. The simulation result shows about 35% reduction of circuit area and 10% lower energy consumption in comparison with that in prior work. In addition, the Error-Free write operation under process variation of both the CMOS transistor and the STT-MTJ is achieved due to its large sense margin ( $\sim 320$ mV).

FTCAM: An Area-Efficient Flash-Based Ternary CAM Design

This paper presents a Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, and a single TCAM cell utilizes 17 transistors. In contrast, our TCAM cell utilizes only two flash transistors, thereby significantly reducing circuit area. We cover the chip-level architecture of the TCAM IC briefly, focusing mainly on the TCAM block which does fast parallel IP routing table lookup. Our flash-based TCAM (FTCAM) block is simulated in SPICE, and we show that it has a significantly lowered area compared to a CMOS based TCAM block, with a speed that can meet current ( $\sim$ 400 Gb/s) data rates that are found in the internet core.

Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT).We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital signal-processing circuits: the Delta Sigma sum adder, average adder and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by MATLAB simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18-μm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future IoT circuits.

A High Performance Delta-Sigma Modulator for Neurosensing.

Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-μm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 μW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

A new hardware-efficient algorithm and reconfigurable architecture for image contrast enhancement.

Contrast enhancement is crucial when generating high quality images for image processing applications, such as digital image or video photography, liquid crystal display processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a novel hardware-oriented contrast enhancement algorithm which can be implemented effectively for hardware design. In order to be considered for hardware implementation, approximation techniques are proposed to reduce these complex computations during performance of the contrast enhancement algorithm. The proposed hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyzes. To decrease hardware cost and improve hardware utilization for real-time performance, a reduction in circuit area is proposed through use of parameter-controlled reconfigurable architecture. The experiment results show that the proposed hardware-oriented contrast enhancement algorithm can provide an average frame rate of 48.23 frames/s at high definition resolution 1920 × 1080.

TUNABLE ACTIVE FILTERS FOR RF AND MICROWAVE APPLICATIONS

In this paper, we present a low-voltage tunable active filter for microwave applications. The proposed filter is based on a single-transistor active inductor (AI), that allows the reduction of circuit area and power consumption. The three active-cell bandpass filter has a 1950 MHz center frequency with a -1 dB flat bandwidth of 10 MHz (Q ≈ 200), a shape factor (30–3 dB) of 2.5, and can be tuned in the range 1800–2050 MHz, with constant insertion loss. A dynamic range of about 75 dB is obtained, with a P1dB compression point of -5 dBm. The prototype board, fabricated on a TLX-8 substrate, has a 4 mW power consumption with a 1.2 V power supply voltage.

32 Bit $\times\,$32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler

In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the user's requirements (e.g., throughput), a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency. Adapting to the run-time workload of the targeted application, razor flip-flops together with a dithering voltage unit then configure the multiplier to achieve the lowest power consumption. The single-switch dithering voltage unit and razor flip-flops help to reduce the voltage safety margins and overhead typically associated to DVS to the lowest level. The large silicon area and power overhead typically associated to reconfigurability features are removed. Finally, the proposed novel MP multiplier can further benefit from an operands scheduler that rearranges the input data, hence to determine the optimum voltage and frequency operating conditions for minimum power consumption. This low-power MP multiplier is fabricated in AMIS 0.35- μm technology. Experimental results show that the proposed MP design features a 28.2% and 15.8% reduction in circuit area and power consumption compared with conventional fixed-width multiplier. When combining this MP design with error-tolerant razor-based DVS, PP, and the proposed novel operands scheduler, 77.7%-86.3% total power reduction is achieved with a total silicon area overhead as low as 11.1%. This paper successfully demonstrates that a MP architecture can allow more aggressive frequency/supply voltage scaling for improved power efficiency.

(Invited) Development of Novel Three-Dimensional Structuring of Integrated Circuits by Using Low Temperature Direct Bonding for CMOS Image Sensors

Recent demands are escalating for higher density of 3D ICs. Stacked CMOS image sensors [1], for example, reduce their pixel footprints down to a few μm2, and interconnection between individual FETs on different layers is needed to integrate 3D ICs into such a small area. Various approaches of 3D IC have been reported, as listed in Table 1 [2-4]. Although through silicon via (TSV) approaches are most common [2], it is unsuitable for local interconnection due to its large diameter (> 5 μm). Approaches based on the sequential integration [3] and silicon-on-insulator (SOI) assembly [4] are also promising. However, penetrating vias for interconnection are required outside the FET areas, limiting the density and free wiring layout.To overcome these problems, we have developed a novel 3D structuring process as shown in Fig. 1. In this process, (a) FETs were formed on the FD (fully-depleted) SOI wafers [5]. (b) Intermediate SiO2 layer was patterned, and Au layer was formed by electroplating. (c) Damascene process by chemical mechanical polishing (CMP) was applied to form Au/SiO2 hybrid surface. (d) After chip-dicing into a 20-mm-square size, Ar and O2 plasma were sequentially performed for surface activation. (e) Two chips were directly bonded at a force of 2000 N for 60 min at 200 °C. Fig. 2 (a) shows the photograph of the Au/SiO2 surface after CMP. Average roughness of the SiO2 was 0.15 nm. Minimum diameter of the Au bonding electrodes was 3 μm. Fig. 2 (b) shows the cross-sectional image, where no void in bonded interface is observed.To demonstrate the availability of the 3D structuring, a 3D CMOS inverter was developed, where NFET and PFET in separate layers were bonded to each other as illustrated in Fig. 3, which reduced circuit area. As this method separates the NFET and PFET processes, both processes could be optimized independently in respective wafers, enabling us to make ideal channels for NFET and PFET in the advanced CMOS processes.Experimentally obtained characteristics of the developed 3D CMOS inverter with 3-μm-diameter Au electrodes are shown in Fig. 4. The figure compares the results with those of the 2D chip developed at the same time, which confirms that the bonding gives no degradation in the IC performance. To confirm the yield of interconnection bonding, a 3D ring oscillator with 101 stages of CMOS inverters was also developed from the NFETs and PFETs made on separate wafers. Oscillation frequency at 1.8 V was observed at 700 kHz as shown in Fig. 5.In summary, 3D structuring technology with excellent suitability for high-density integration was successfully demonstrated by applying Au/SiO2 hybrid bonding. The developed process is promising for the highly integrated stacked CMOS image sensors and More-than-Moore type devices for the next generation.

MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder

Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding (AVC). This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition (HD) video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video. Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding (AVC). This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition (HD) video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video.

Compact Microstrip Filtering Power Dividers With Good In-Band Isolation Performance

Compact and high isolation microstrip filtering power dividers (PDs) have been presented in this letter. In order to effectively reduce circuit area, the compact folded net-type resonator is selected to build up the resonator-based PDs with a filtering response. The highly symmetric structure of the divider provides not only a good in-band isolation performance, but also a low magnitude imbalance and phase imbalance. For the demonstration, two design examples of in-phase and out-of-phase PDs with second-order Chebyshev filtering response have been designed and fabricated with microstrip technology. As a result, both dividers have an extremely small size of 0.19 λg by 0.19 λg. The measured results are in good agreement with the simulated predictions, showing that better than 30 dB isolation within the whole passband is achieved with a tradeoff of the bandwidth.

Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic

We present a novel approach for matching the drive current of n-FET with p-FET in CMOS logic circuits through source-drain extension profile tuning. Our approach overcomes the current quantization issue in nanowire/FinFET devices. We show that, in comparison to conventionally used method, where the width of p- device is increased to match the drive of n-device, the proposed approach provides significant reduction in circuit area and power consumption. When compared to the high-performance CMOS inverter (current matched using device width), the proposed method shows 28% lower area and 38% saving in power in case of Si-nanowire CMOS inverter. Further, the technique is applicable to planar CMOS showing excellent gain.

VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

Spectrally efficient FDM (SEFDM) systems employ non-orthogonal overlapped carriers to improve spectral efficiency for future communication systems. One of the key research challenges for SEFDM systems is to demonstrate efficient hardware implementations for transmitters and receivers. Focusing on transmitters, this paper explains the SEFDM concept and examines the complexity of published modulation algorithms, with particular consideration to implementation issues. We then present two new variants of a digital baseband transmitter architecture for SEFDM, based on a modulation algorithm which employs the discrete Fourier transform (DFT) implemented efficiently using the fast Fourier transform (FFT). The algorithm requires multiple FFTs, which can be configured either as parallel transforms, which is optimal for throughput or using a multi-stream FFT architecture, for reduced circuit area. We propose a simplified approach to IFFT pruning for pipeline architectures, based on a token-flow control style, specifically optimized for the SEFDM application. Reconfigurable implementations for different bandwidth compression ratios, including conventional OFDM, are easily derived from the proposed implementations. The SEFDM transmitters have been synthesized, placed and routed in a commercial 32 nm CMOS process technology and also verified in FPGA. We report circuit area and simulated power dissipation figures, which confirm the feasibility of SEFDM transmitters.

Miniaturized size of dual‐band‐meandered branch‐line coupler for WLAN application

AbstractA new method of a dual‐band miniaturized branch‐line coupler (BLC) is presented with two widely separated bands (f2 > 2f1) for wireless local area network application. Partially meandered lines are used as the coupler's shunt arms; and are designed to operate at f1 = 2.45 GHz and f2 = 5.8 GHz. There are 65 and 90% reduction in circuit area compared to the previous research design. Theoutput signal ports have an equal power split within measurement accuracy and 2° error at the resonant frequencies. The simulated and measured results are in good agreement, thereby verifying the design concept. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2543–2547, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26312