Reduced Power Supply Research Articles

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

AbstractPower dissipation is a main attention for designing complementary metal oxide semiconductor Very Large Scale Integration (VLSI) circuits in deep sub‐micron technology. Constant field device scaling leads to high transistor density, reduction in power supply, lower threshold voltage, and reduction in oxide thickness. This gives rise to short channel effects and increases the leakage currents causing power dissipation. In this paper, based on literature survey, new flipped drain gating (FDG) technique is proposed for mitigation of leakage currents; further FDG technique is integrated with power gating technique which makes power dissipation lower than FDG. Proposed techniques are integrated with FinFET technology and applied on Logic Gates and bench mark circuits on HSPICE simulator. Simulation is carried out at 27°C temperature by using 20 to 7‐nm Berkley Predictive Technology Module. Simulation results at 10‐MHz frequency shows maximum saving in leakage power using FDG technique at input vector 01 as 80.35% compared with conventional drain gating for EXOR logic. Similarly, FDG technique saves maximum dynamic power of 25.98% when compared with conventional drain gating for AND logic.

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.

Power supply risk assessment method for relay protection system faults

Abstract The influence and the potential risk due to hidden faults of a relay protection system on power supply in distribution systems are paid more and more attention to. A probability analysis method is used to analyse fault characteristics and action mechanism of dominant faults, hidden misoperation and non-operation of the relay protection systems, and failure probability model of relay protection system is constructed and simplified. The effects of dominant faults, hidden misoperation and non-operation of the relay protection systems on the reduced power supply load power are analysed, and a probabilistic model for reduced power supply load power is constructed by three parts corresponding to dominant faults, hidden misoperation and non-operation. A probability calculation method of power supply risk occurrence due to hidden faults of relay protecttion system is proposed considering the fault probability of the relay protection systems, the frequency of the hidden faults occurring in operation period, the reduced power supply load power or load power outage, and the connection mode of the in-lines, out-lines and transformers in a substation. The feasibility and applicability of the proposed method for estimation of risk value probability of the relay protection systems is verified by two studied examples.

Proteomic and metabolomic analyses reveal metabolic responses to 3-hydroxypropionic acid synthesized internally in cyanobacterium Synechocystis sp. PCC 6803.

Background3-hydroxypropionic acid (3-HP) is an important platform chemical with a wide range of applications. In our previous study, the biosynthetic pathway of 3-HP was constructed and optimized in cyanobacterium Synechocystis sp. PCC 6803, which led to 3-HP production directly from CO2 at a level of 837.18 mg L−1 (348.8 mg/g dry cell weight). As the production and accumulation of 3-HP in cells affect cellular metabolism, a better understanding of cellular responses to 3-HP synthesized internally in Synechocystis will be important for further increasing 3-HP productivity in cyanobacterial chassis.ResultsUsing a engineered 3-HP-producing SM strain, in this study, the cellular responses to 3-HP internally produced were first determined using a quantitative iTRAQ-LC–MS/MS proteomics approach and a LC–MS-based targeted metabolomics. A total of 2264 unique proteins were identified, which represented about 63 % of all predicted protein in Synechocystis in the proteomic analysis; meanwhile intracellular abundance of 24 key metabolites was determined by a comparative metabolomic analysis of the 3-HP-producing strain SM and wild type. Among all identified proteins, 204 proteins were found up-regulated and 123 proteins were found down-regulated, respectively. The proteins related to oxidative phosphorylation, photosynthesis, ribosome, central carbon metabolism, two-component systems and ABC-type transporters were up-regulated, along with the abundance of 14 metabolites related to central metabolism. The results suggested that the supply of ATP and NADPH was increased significantly, and the precursor malonyl-CoA and acetyl-CoA may also be supplemented when 3-HP was produced at a high level in Synechocystis. Confirmation of proteomic and metabolomic results with RT-qPCR and gene-overexpression strains of selected genes was also conducted, and the overexpression of three transporter genes putatively involved in cobalt/nickel, manganese and phosphate transporting (i.e., sll0385, sll1598 and sll0679) could lead to an increased 3-HP production in Synechocystis.ConclusionsThe integrative analysis of up-regulated proteome and metabolome data showed that to ensure the high-efficient production of 3-HP and the normal growth of Synechocystis, multiple aspects of cells metabolism including energy, reducing power supply, central carbon metabolism, the stress responses and protein synthesis were enhanced in Synechocystis. The study provides an important basis for further engineering cyanobacteria for high 3-HP production.Electronic supplementary materialThe online version of this article (doi:10.1186/s13068-016-0627-6) contains supplementary material, which is available to authorized users.

A novel Li-ion battery charger using multi-mode LDO configuration based on 350 nm HV-CMOS

The design of a novel Li-ion battery charger using multi-mode LDO architecture has been introduced in this paper. The proposed architecture, using an improved multi-mode LDO, not only obtains high accuracy but also reduces power supply noise because of utilizing novel error amplifier and power buffer configuration; while still consuming low power dissipation. To obtain the low power consumption, the Schmitt Trigger technique is applied to the charging controller and an optimized current driven circuit is proposed. Besides, the PSRR parameter is also enhanced by adding pre-regulation circuit in multi-mode LDO circuit. Thus, the proposed Li-ion battery charger achieves 700 mA operation current with 70.9 % efficiency but only dissipates 495 mW in power. During the charging process, the setting time and ripple issues are solved by the use of soft-start circuit which is integrated into the charging controller in order to decrease the chip area. Therefore, the setting time is reduced to 5.5 μs while gaining the load regulation at approximately 0.019 μV/mA and increasing PSRR up to 106 dB at DC level. Moreover, the line regulation is also reduced at 1.3 mV/V. The proposed linear battery charger is designed and implemented, based on High-Voltage CMOS process with using 4.5 V power supply voltage and obtaining 4.2 V battery output voltage.

Study of high-tech process furnace using inherently safer design strategies (III) advanced thin film process and reduction of power consumption

Semiconductor manufacturing is the economic backbone of Taiwan. Although efforts have been made to improve production capacity and achieve full load production, manufacturers are still unable to effectively control the power consumption situation during the failure of full load production due to special circumstances. Those processes do not conform to the characteristics of inherently safer design, which increases process risks. The objective of this research was to investigate the effects of power consumption reduction on the process furnace, maintaining the same production capacity in the existing 22 nm advanced semiconductor process. In this study, TEOS was used as the raw material for LPCVD process simulation, experimentation, and exploration. The adopted LPCVD reactor was of the commercial batch type; the process experiments simulated the IPD process applied on the 22 nm MOSFET, with a thickness of 5000 Å and process time of 60 min. The simulation results of different batches were compared with the experimental values, and the simulation values were consistent with the experimental values by adjusting the different ka values. The reactor contained processes for 125 wafers and 100 wafers. According to the simulation and experimental results, the thin film deposition results were acceptable. Finally, the heating zone output current was explored specifically for two batches of wafers in the 12″ furnace tube process. In the process of the first batch, as there were only 100 wafers, 18.05 A was reduced by shutting off the 5th heating zone. The machine had a voltage of 220 V and converted power output up to 3971 W, accounting for 26% (15265.8 W) of the entire machine. This significantly reduced power supply of the entire machine and hazard potential, which is consistent with the characteristics of inherently safer design. Moreover, there were fifteen 12″ tube furnace machines in the experimental workshop of this study, and shutting off unnecessary heating zones could reduce 59565 W/H of the power supply and hazard potential. Finally, the 12″ tube film process machine electrical hazards and damage control measures were analyzed by using FMEA method, and confirmed that the research results were in line with the expected attenuation strategy of ISD. This approach has increased the safety level, but also reduced operating costs, which is an important achievement of this study.

LCNT-an approach to minimize leakage power in CMOS integrated circuits

Leakage power dissipation is the dominant contributor of total power dissipation in nanoscale complementary metal oxide semiconductor (CMOS) integrated circuits. CMOS technology scaling demands for a reduced power supply, low threshold voltage, high transistor density and reduced oxide thickness, which has led to significant increase in leakage power especially during standby mode. Here in this paper, at first we review some of the existing techniques for leakage minimization and pointed out their merits and shortcomings. We then propose a novel transistor level approach called leakage control NMOS transistor (LCNT) for leakage minimization. The proposed technique inserts two leakage control transistors (all N-type) within a standard CMOS logic circuit. The gate terminal of the leakage control transistors are connected with the drain of the pull-up transistors. Performance of the proposed technique is investigated in terms of area, power, delay, and power-delay product applying on some basic gates and benchmark circuits. The performance metrics of the proposed LCNT are then compared with other existing techniques. Extensive SPICE simulations were carried out using 32 nm predictive technology model. Simulation results indicate that the proposed technique is quite efficient in minimizing the leakage power which is found out to be 48.4 %.

Analysis of Synchronous Buck Converter with ANFIS Controller for Industrial

Design of low compact power supply unit in microprocessor is become a major demand from modern computer manufacturing industries. Voltage Regulator Module enforced major design requirement for the effective power supply in processors. One of the challenging power management system is the analysis of VRM to meet the new specification opted by the modern industries. The present study is carried out to analyze the VRM and meet the recent requirements such as performance of customer equipment (processors and computers) and DC-DC converter under reduced power supply. For the improvement of speed and voltage fluctuation, Synchronous (SR) Buck Converter with ANFIS controller are analyzed. Among the other soft computing techniques, ANFIS (Adaptive Neuro Fuzzy Inference System) gives significant results. Due to the dynamic nature of the load current, the efficient energy conversion is not possible. But the advancements in the areas of artificial intelligence have made it feasible to beat the hurdles. The SR Buck converter adopting the advantages of ANFIS has been proved to be more successful with the fast dynamic response with high accuracy. The complete system is modeled using MATLAB/SIMULIK.

RETRACTED: A New Method to Energy Saving in a Micro Grid

Optimization of energy production systems is a relevant issue that must be considered in order to follow the fossil fuels consumption reduction policies and CO2 emission regulation. Increasing electricity production from renewable resources (e.g., photovoltaic systems and wind farms) is desirable but its unpredictability is a cause of problems for the main grid stability. A system with multiple energy sources represents an efficient solution, by realizing an interface among renewable energy sources, energy storage systems, and conventional power generators. Direct consequences of multi-energy systems are a wider energy flexibility and benefits for the electric grid, the purpose of this paper is to propose the best technology combination for electricity generation from a mix of renewable energy resources to satisfy the electrical needs. The paper identifies the optimal off-grid option and compares this with conventional grid extension, through the use of HOMER software. The solution obtained shows that a hybrid combination of renewable energy generators at an off-grid location can be a cost-effective alternative to grid extension and it is sustainable, techno-economically viable, and environmentally sound. The results show how this innovative energetic approach can provide a cost reduction in power supply and energy fees of 40% and 25%, respectively, and CO2 emission decrease attained around 18%. Furthermore, the multi-energy system taken as the case study has been optimized through the utilization of three different type of energy storage (Pb-Ac batteries, flywheels, and micro—Compressed Air Energy Storage (C.A.E.S.).

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS

In this paper, a data-jitter mixing (DJM) forwarded-clock receiver is proposed that achieves high jitter correlation between data and a clock for high speed and small power consumption. The first-stage injection-locked oscillator (ILO) filters out high-frequency clock jitter that loses the correlation due to a latency mismatch between data and the clock. Then, a data-jitter mixer in the second stage of the proposed receiver further increases the jitter correlation reduced by nonoptimal jitter filtering in ILO. Moreover, the DJM reduces power supply noise induced jitter from a clock distribution network, while the conventional jitter filter cannot track the high-frequency jitter because of filtering it out. A prototype receiver implemented in 1-V 65-nm CMOS process achieves 9.6 Gb/s with 1.22-mW/Gb/s in spite of a 1.92-ns latency mismatch between data and a clock.

The development experience of the laboratory stand for comparative analysis of the sources energy efficiency of the artificial lighting

In order to increase the level of knowledge in the field of energy efficient systems and technologies at the Department of Electromechanics SHEI Kryvyi Rih National University the laboratory Energy efficient devices and technologies in electromechanics was put into operation.One of the developed stands presented in a laboratory is designed for analysis of the artificial light sources characteristics. The stand consists of two identical modules for analyzing of the lamp characteristics and the control module, which is designed to control and reference modes of the lamps and electrical parameters measurements of the light sources. It is offered a rather simple method of the ratio calculating of luminous efficiency, based on the measured values averaging of illumination at points located on the arc of the constant radius. The realization of the researches does not require any expensive equipment.Currently, four laboratory works are executed on the stand: definition and comparison of the luminous efficiency ratio of the lamps of general and industrial purpose; compensation of the reactive power, which is consumed by the gas-discharge lamps with the induction ballast; definition and analysis of the ripple factor of the lamps luminous flux; identification and analysis of the luminous efficiency ratio changes of the incandescent lamps by the reducing power supply voltage.Conducted research has shown a sufficient degree of coincidence of the obtained results with the averaged Internet values.The stand implies the possibility of further upgrading and increasing the number of performed laboratory works.

Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS

It is traditionally challenging to implement higher-order PWM closed-loop Class-D audio amplifiers using analog intensive techniques in deep-submicron, low voltage process technologies. This is primarily attributed to reduced power supply, degraded analog transistor characteristics, including short-channel effects, increased flicker noise, random telegraph noise, transistor reliability concerns and passive component performance. In this paper, we introduce a global closed-loop mixed-signal architecture incorporating digital control and integrate a fourth-order amplifier prototype in 55 nm CMOS. A systematic approach to analyze, design and compensate the feedback loop in the digital domain is also presented. The versatility of implementing the loop gain poles and zeros digitally attains high gain throughout the audio band and attenuates residual high frequency ripples around the loop, simultaneously accomplishing improvements in THD+N and PSRR. The overall architecture is inherently amenable to implementation in deep-submicron and is therefore compatible with scaled CMOS. The measured prototype achieves a high 105 dBA SNR, 0.0031% THD+N, 92 dB PSRR and 85% efficiency when supplying 1 W into emulated 8 $\Omega$ speaker load. This performance is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies and reports the highest output power (1.5 W) for deep-submicron designs.

DESIGN OF LOW VOLTAGE LOW POWER OPERATIONAL AMPLIFIER

This Thesis presents a design of the Folded-cascade operational amplifier which leads to high gain as compared to a normal cascade circuit. In this project; specifications of analog systems into op amp level net-lists of library components is studied and simulated using XILINX. As the power-supply voltages because of the technology improvement and it are desired to reduce power supply to minimize power dissipation, many challenges are faced by the analog designer. One is to keep noise level as possible. The op-amp must be designed to with the ever decreasing power supply voltages. As the power supply voltages begin to approach 2Vt, new technique and new op-amp topology like folded cascade should be used.

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC

By integrating multiple processing units (PUs) and memories on a single chip, multiprocessor system-on-chip (MPSoC) can provide higher performance per energy and lower cost per function to applications with growing complexity. On the other hand, shrinking feature sizes and reducing power supply voltages also make MPSoCs more susceptible to various reliability threats, such as power/ground (P/G) noises. Power gating is an effective technique to minimize leakage power. However, it also introduces significant P/G noises in MPSoCs. With significant area, power and performance overheads, traditional methods rely on reinforced circuits or fixed protection strategies to reduce P/G noises caused by power gating. In this paper, we propose a systematic approach to actively alleviating P/G noises using the parasitic capacitance of on-chip memories through sensor network on-chip (SENoC). We use the parasitic capacitance of on-chip memories as dynamic decoupling capacitance to suppress P/G noises and develop a detailed HSPICE model for related study. SENoC is developed to not only monitor and report P/G noises, but also coordinate PUs and memories to alleviate such transient threats at run time. Extensive evaluations show that compared with traditional method, our approach saves 12.6%–62.8% energy consumption and achieves 14.3%–69.8% performance improvement for different applications and MPSoCs with different scales. We implement the circuit details of our approach and show its low area and energy consumption overheads.

Design of RF Low Noise Amplifier at 2GHz in 0.18µm Technology

a 2Ghz Low Noise amplifier (LNa) has been implemented in Cadence spectre RF tool on UMC 0.18μm technology and is designed using a modified Cascode topology to work under reduced power supply. The input and output matching network is matched to 50Ω. after simulation it is found that at resonance frequency of 2Ghz, the forward gain is 18.22dB and reverse isolation is -40.86dB.

Design and optimization of impurity- and electrostatically-doped superlattice FETs to meet all the ITRS power targets at VDD = 0.4 V

In this work full-quantum simulations have been employed to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) superlattice FETs (SL-FETs). A sensitivity investigation to technological and design parameters has been carried out, showing a relatively-low sensitivity to changes of most device parameters. Results at a reduced power supply VDD=0.4V are compared with the ITRS specs projected to year 2022. Benchmarking highlights the potential of the proposed ED InGaAs/InAlAs SL-FET to perform up to 1.2× faster than HP specs with 5× lower energy-delay product. This device is thus expected to be a good candidate for the post-CMOS era.

ENHANCEMENT IN POWER-DELAY PRODUCT BY DRIVER AND INTERCONNECT OPTIMIZATION

To obtain higher performance with maximum devices and smaller chip size semiconductor devices are continuously shrinking. However, leakage power dissipation increases significantly with the technology scaling. Increasing demand for ultra low power devices has increased significantly since last decade and it compels advance technological solutions to fulfill power requirements of electronic appliances. As a result subthreshold operation region and different device optimization techniques attracts different researchers to achieve ultra low power design of VLSI circuits. Power supply reduction is supposed to be the main parameter to reduce power reduction. However, deep subthreshold region offers speed penalty degrading the overall performance of a device which suggests the need for optimizing device parameters. This paper analyzes the driver and interconnects performance by changing threshold voltage (Vth) and oxide thickness (Tox) in subthreshold region. Further, it also compares the optimized driver performance and DTMOS driver performance at 0.4 V. Moreover, a large amount of gain in performance was observed when optimized interconnect is used with the optimized driver. Result shows that performance of a circuit enhances if the optimized driver is used compared to DTMOS driver.

Associative memory architecture for word-parallel smallest Euclidean distance search using distance mapping into clock-number domain

A scalable word-parallel associative memory for smallest Euclidean distance (ED) search is presented. Due to the applied concept of distance to clock-number mapping, the reported architecture is digital in nature and scalable to advanced technology. Furthermore, the reference data of feature vectors can be scaled in principle to any vector dimension and number. Handling of the numerical complexity of the ED without large consumption of Silicon area is achieved by an area-efficient circuit, which uses the same adder for absolute-difference calculation of vector components and subsequent square calculation by sequential addition of partial products. Additionally, a clock-number minimization algorithm is proposed to significantly reduce the clock-number needed for the search when the smallest ED is a large value. The concept of the proposed architecture has been experimentally verified by measurement results from real chips fabricated in a 180 nm CMOS technology, in which the architecture is configured for parallel smallest ED search among 32 reference vectors with each vector having 16 8-bit elements. For the application example of codebook-based data compression, the fabricated test chip achieved 1.19 µs average search time, 5.77 µs worst-case search time and low power consumption of 8.75 mW at the maximum clock frequency of 47 MHz and nominal power supply voltage Vdd = 1.8 V. At reduced power supply voltage Vdd = 1.2 V, a smaller power consumption of 2.80 mW at an also smaller maximum clock frequency of 24 MHz is measured. In comparison to previous analog–digital architecture, a reduction of the normalized power-delay product per matching operation by about a factor 1.6 at Vdd = 1.8 V (about factor 2.5 at Vdd = 1.2 V) is obtained with best-case data for the analog–digital architecture and average-case data for the proposed fully-digital architecture.

Voltage Dependency of Propagating Single-Event Transient Pulsewidths in 90-nm CMOS Technology

This paper reports on the supply voltage dependency of single-event transient (SET) propagation and multinode charge collection phenomena in integrated circuits. We have found that the SET pulsewidth propagating to subsequent stages in a circuit may decrease with reduced power supply voltage, which runs counter to the general conclusion that ultralow power applications are much more susceptible to disruption from a particle strike. This effect provides the circuit designers a guidance to reconsider the impact of voltage on SET pulsewidth.

Near-Threshold CNTFET SRAM Cell Design With Word-Line Boosting and Removed Metallic CNT Tolerance

In this study, we report an in-depth study of power supply reduction toward near threshold for an eight-transistor carbon nanotube (CNT) field-effect transistors SRAM cell. Near-threshold voltage has an impact on delays, energy, energy-delay product, leakage current, and static noise margin. In addition, we have incorporated a removed metallic CNT approach to deal with nonsemiconductor CNTs. Monte Carlo simulations at Vdd (power supply voltage) of 0.4 V have shown that 97.24% of the cells are functional after removing the metallic CNTs. The power saving is over 5× and the average delay is increased by 3.5× as compared to a typical Vdd of 0.9 V. To further improve yield and performance, a word-line boosting technique is explored. Read and write word lines are boosted with additional 100 mV; this in turn effectively eliminates all the write failures at the 0.4 V level and reduces read and write delays. Comparing boosted and nonboosted cells with Vdd = 0.4 V, the boosted cell has write and read delays that are faster by 3.8× and 1.7×, respectively. This cell's energy increases by less than 4% per-access in the worst case. The cell with Vdd of 0.4 V with boosted word-lines achieves the lowest energy-delay product of all the cases considered in this study, which is 52.3% and 56.9% lower than that of a boosted and nonboosted cell with Vdd of 0.9 V, respectively.