Near-Threshold CNTFET SRAM Cell Design With Word-Line Boosting and Removed Metallic CNT Tolerance

Abstract

In this study, we report an in-depth study of power supply reduction toward near threshold for an eight-transistor carbon nanotube (CNT) field-effect transistors SRAM cell. Near-threshold voltage has an impact on delays, energy, energy-delay product, leakage current, and static noise margin. In addition, we have incorporated a removed metallic CNT approach to deal with nonsemiconductor CNTs. Monte Carlo simulations at Vdd (power supply voltage) of 0.4 V have shown that 97.24% of the cells are functional after removing the metallic CNTs. The power saving is over 5× and the average delay is increased by 3.5× as compared to a typical Vdd of 0.9 V. To further improve yield and performance, a word-line boosting technique is explored. Read and write word lines are boosted with additional 100 mV; this in turn effectively eliminates all the write failures at the 0.4 V level and reduces read and write delays. Comparing boosted and nonboosted cells with Vdd = 0.4 V, the boosted cell has write and read delays that are faster by 3.8× and 1.7×, respectively. This cell's energy increases by less than 4% per-access in the worst case. The cell with Vdd of 0.4 V with boosted word-lines achieves the lowest energy-delay product of all the cases considered in this study, which is 52.3% and 56.9% lower than that of a boosted and nonboosted cell with Vdd of 0.9 V, respectively.