Reduced Switch Count Research Articles

Enhancing Reliability in Multilevel Inverter: A Fault‐Tolerant Approach With Reduced Switch Count

ABSTRACTReliability is a major concern in multilevel inverters (MLI) due to the increased number of power switches and diodes, which increases the chance of switch failures and complicates the inverter design. The primary challenges faced by the current MLI design include higher control complexity, increased parasitic elements, more extensive protection, and lack of multiple fault tolerance. Therefore, developing reduced switch MLI with fault‐tolerant ability is crucial to ensure system availability and prevent adverse outcomes. To address these challenges, this article introduces a highly resilient fault‐tolerant reduced switch count (FTRSC) MLI topology offering fault tolerance with minimal switch count. The proposed topology provides fault tolerance in case of single‐ and multiple‐switch open‐circuit (OC) failures. The inherent fault‐tolerant operation is analyzed for the proposed topology's symmetric and asymmetric configurations. The simulation and experimental results validate the effectiveness of the proposed topology considering normal, faulty, and postfault conditions. Furthermore, the reliability evaluation of the proposed work is carried out using the Markov chain model, resulting in a high total mean time to failure of approximately 117,550 h/failures, along with an efficiency of 96.3%. These findings demonstrate that the proposed circuit has enhanced reliability and extended mean time to failure, affirming its suitability for sensitive industrial applications. Finally, a thorough comparison with recent studies highlights the superiority of the proposed system.

Power and efficiency enhancement of solar photovoltaic power plants through grouped string voltage balancing approach

Solar photovoltaic (PV) power plants’ performance is severely impacted by multi-level irradiances or partial shading, leading to power losses and voltage instability. Also, partial shading adds further complexity to the maximum power point tracking algorithms by introducing numerous peaks in the power curves, resulting in additional losses. Numerous solutions are presented to deal with shading losses, and dynamic reconfiguration is the most effective; however, higher switch count and complex architecture make it impractical in real-world implementation. Hence, this study proposes a low-complexity architecture based on the grouped string voltage balancing approach. This approach utilizes a voltage balancing converter connected to groups of strings to enhance the power output of the array of PV plants, maintain overall system voltage stability, and eliminate the possibility of multiple peaks formation in the power curves. The effectiveness of the proposed approach is tested under numerous static and dynamic partial shadings and analyzed using power curves, power output, losses, efficiencies, and voltage stability. The validation is done by comparing the proposed approach with conventional and advanced architectures for a 32.5 kW system. The results show that the proposed method requires a 50 % reduced switch count than existing techniques, achieves 99.54 % efficiency, and maintains an average voltage stability of 0.01.

Performance Investigation of 17 Level Reduced Switch Count Multilevel Inverter

The primary objective of this paper is to introduce a 17-level multilevel inverter with only eight power switches and three diodes that can be suitable for electric vehicle applications. This setup utilizes three distinct unequal DC sources to create the 17 levels of output voltage waveforms. The modes of operations of the proposed topology have been discussed in detail. The calculation of conduction losses, switching losses, efficiency, total standing voltage, and cost function per level for the suggested inverter has been elaborated. Due to more semiconductor power switches, diodes, capacitors, driver circuits, and DC sources in typical inverters, switching losses, costs, and harmonic distortion are increased. The nearest-level control technique has been utilized to control the switching elements of the recommended configuration. The performance comparison of various multilevel inverter topologies has also been discussed. The suggested multilevel inverter provides a higher efficiency of 98.60%, cost function of 3.6 for a weight coefficient of 1, improved power quality, and higher reliability. A reduction in the power switches significantly reduces the convolution of switching circuitry. The total harmonic distortion produced by this inverter is 3.49%, which comes under the IEEE standard of 5%.

Solar PV based seventeen level reduced switch symmetrical multilevel inverter topology fed induction motor

Multilevel inverters have received a lot of interest in recent years due to their ability to deliver more voltage levels than typical two-level inverters. Because of this property, multilevel inverters can produce output waveforms that closely resemble sinusoidal waveforms, lowering harmonic distortion dramatically. The emergence of reduced switch symmetrical multilevel inverter topologies has developed the curiosity of many different power conversion systems. These new topologies offer numerous advantages, including greater output voltage quality, fewer harmonic distortions, and increased power conversion efficiency. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. A 17 levels of multi-level inverter (MLI) topology is presented with reduced switch count and harmonic reduction for power quality improvement. The inverter is fed by isolated equal photovoltaic panels which act as direct current or DC source. To reduce complexity, switching pulses are generated using hybrid pulse width modulation technique which is designed as controller. Through the use of MATLAB/Simulink, the performance assessment of a unique cascaded multilevel inverter-based reduced switch symmetrical inverter feeding an induction motor drive has been verified. The harmonic distortion with reduced switches obtained is 7.47% which is comparatively less than when compared with conventional cascaded H-bridge topology.

15-Level Inverter Topology of Reduced Switch Count With Power Loss Analysis

A multi-level inverter surpasses the capabilities of a traditional inverter, have developed to accommodate voltage applications and finding widespread commercial use. While conventional inverters yield the output in the shape of a square, inverters with multilevel are employed to generate a waveform that closely approximates a sinusoidal one. In comparison to traditional inverters, the 15-level inverter exhibits advantages such as reduced THD, the power quality of output power is improved by using the DC link with higher voltages, and switching losses are reduced. Multilevel inverters achieve these benefits by utilizing a smaller number of switches and generate closer to sinusoidal output. This particular approach involves the use of ten switches to generate output of 15 levels, contributing to a simplified circuit design.

Nine-Switch Multiport Converter Applied to Battery-Powered Tramway with Reduced Leakage Current

Electrically powered rail transport is constantly increasing in order to meet the high demand for people and cargo transportation, whether with high-speed trains, subways, suburban trains, or electric tramways. In these types of applications, power electronics solutions such as integrated and efficient converters with multiple functionalities are highly desirable. Among these converters, one family stands out for its ability to generating multiple output terminals with reduced number of switches, namely, the nine-switch converter. Therefore, this paper proposes a multiport converter solution based on the nine-switch converter topology that integrates multiple functionalities with a reduced switch count. The converter, responsible for the power drive of the electric tramway, is exclusively powered by a battery. Moreover, it presents a strategically connected passive filter that provides a low-impedance path for high-frequency currents, avoiding leakage of the current circulation in the induction motor. Its phase-shift pulse-width modulation is capable of reducing the high-frequency components of the current delivered by the battery. The energy storage system is designed to optimize the system capacity based on the known real load profile of a public tramway, with a maximum power of 532.1 kW. The control system is designed and applied considering the battery as the energy source. Simulations were performed in the Matlab/Simulink environment to validate the proposed system, along with experiments using a reduced-scale prototype controlled by the dSPACE platform. The results present the converter’s proper operation with integration of the source and AC load, presenting improved features compared with conventional solutions in terms of reduced leakage of the current circulation from the AC load and reduced battery current ripple.

A Reduced Switch Count Five Level Inverter With Extended Linear Modulation Range Up to Full Base Speed

A Reduced Switch Count Five Level Inverter With Extended Linear Modulation Range Up to Full Base Speed

Fault-Tolerant Analysis Based Performance Assessment of Single-Phase Multilevel Inverter Topologies with Reduced Switch Count

Fault-Tolerant Analysis Based Performance Assessment of Single-Phase Multilevel Inverter Topologies with Reduced Switch Count

A New Symmetrical Cascaded Single Phase H Bridge Inverter With Reduced Switch Count

A New Symmetrical Cascaded Single Phase H Bridge Inverter With Reduced Switch Count

A Novel Seven Level Inverter with Reduced Switch Count and THD for PV System Applications

A Novel Seven Level Inverter with Reduced Switch Count and THD for PV System Applications

A Five-Level Common-Ground Inverter With Reduced Switch Count for Transformerless Grid-Tied PV Applications

A Five-Level Common-Ground Inverter With Reduced Switch Count for Transformerless Grid-Tied PV Applications

A Reduced Switch Count Power Cell for Regenerative Cascaded H-Bridge (CHB) Converter

A Reduced Switch Count Power Cell for Regenerative Cascaded H-Bridge (CHB) Converter

A Multimode On-Board Charger With Multiport Outputs With Reduced Switch Count for EVs

A Multimode On-Board Charger With Multiport Outputs With Reduced Switch Count for EVs

A new reduced switch count symmetrical and asymmetrical modular topology for multilevel inverters

A new reduced switch count symmetrical and asymmetrical modular topology for multilevel inverters

A 3-Phase Reduced Switch Count Symmetric 17-Level Inverter Topology Supplying a Resistive Load

A 3-Phase Reduced Switch Count Symmetric 17-Level Inverter Topology Supplying a Resistive Load

A New Reduced Switch Count Symmetrical and Asymmetrical Modular Topology for Multilevel Inverters

A New Reduced Switch Count Symmetrical and Asymmetrical Modular Topology for Multilevel Inverters

A Fifteen-Level Reduced Switch Count Multilevel Inverter with Multicarrier PWM

A multilevel inverter performs a major role in increasing the range of the level of output voltage without the use of a transformer in the power sector. Here an asymmetrical 15-level multilevel inverter fed from three unequal voltage sources has been proposed. The various modes of the conduction of the eight switches with the switching pattern are discussed with the circuit’s operation. The performance of the circuit is analysed using various techniques under MC-PWM methodologies such as Phase disposition (PD) PWM, Alternate POD (APOD) PWM, and Phase Opposition Disposition (POD) PWM. Key Finding: The logical expression used for generating the pulse pattern of the above techniques using the level shifting PWM technique to reduce the harmonics is performed, simulated, and compared by implementing three techniques for linear and non-linear load. The performance in terms of THD of output voltage under various modulation indexes is compared for various Llvel-shifting techniques. The performance of this 15L-MLI is simulated using MATLAB/Simulink and implemented in a prototype hardware model.

Assessment of hybrid MPPT for SPV based high gain cubic boost converter interfaced with reduced switch multilevel inverter for power quality enhancement

A high-gain cubic boost converter (HG-CBC) with hybrid-based maximum power point tracking (MPPT) through a neural network (NN) aided by the P&O technique (HNN-PO MPPT) has been suggested to acquire optimum power from a solar photovoltaic (SPV) model under varying climatic conditions. The SPV’s output is enhanced using the suggested HG-CBC as per the requirement. A detailed comparison of different conventional boost converters (BC) with the suggested HG-CBC is presented, mainly highlighting part count and boost factor (B). Using the MATLAB tool, the functionality of the developed HNN-PO MPPT technique has been examined for constant and different irradiation (G) levels. The hybrid-based MPPT helps quickly attain maximum power point (MPP) with minimum oscillations at the output. The convergence period is very short with high precision in comparison with P&O and NN MPPT. The results are examined between the suggested and traditional MPPT methods in relation to the percentage of oscillations and rise time. The Reduced Switch Multilevel Inverter (RSMLI) is proposed to integrate the SPV with the RL load. The RSMLI is compared with the conventional standard five-level MLI in relation to the quantity of DC sources, diodes, switches, capacitors, and other parts utilized. The suggested MLI involves a reduced switch count, which mitigates the overall losses during switching and hence improves the efficiency of an inverter. MLI switches are controlled using a sine Pulse Width Modulation (PWM) technique. The THD of the output current of a five-level RSMLI is 4.47%, and it falls within the IEEE 519 norm. Hence, output power quality is enhanced.

21 Level Asymmetric Inverter without Inversion Circuit with Reduced Switch Count for BLDC Motor Drive

21 Level Asymmetric Inverter without Inversion Circuit with Reduced Switch Count for BLDC Motor Drive

An open circuit fault-tolerant seven-level inverter with symmetric sources and reduced switch count

In this study, a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers fewer controlled switches, power diodes, DC sources voltage stress across switches and losses compared with classical and a few recently proposed topologies in the literature. This paper presents a fault-tolerant (FT) seven-level inverter to provide uninterrupted supply to the connected load under open circuit fault in any single switch of the presented configuration. This configuration uses only six unidirectional and one bidirectional switch for any switch fault-tolerant operation. The phase opposition disposition sinusoidal pulse width modulation (POD-SPWM) and phase disposition sinusoidal pulse-width modulation (PD-SPWM) scheme are used for proper DC link utilisation in seven-level output voltage. The proposed symmetrical 7-level topology requires fewer power components and offers reduced voltage total harmonic distortion (THD) compared to other multi-level inverter (MLI) topologies. This MLI is investigated in MATLAB and validated using hardware in the loop platform of OPAL-RT. The obtained results are presented to demonstrate the successful FT operation under any single switch open circuit fault.