Reduced Instruction Set Computer Processor Research Articles

VHDL Design and Synthesis of 64 bit RISC Processor System on Chip (SoC)

The paper presents the design and synthesis of 64 bit Reduced Instruction Set Computer (RISC) on Spartan-3E FPGA. A computer using few instructions with simple constructs so they can be executed at much faster rate within the CPU without having to use the memory very often. This type of computer is classified as a reduced instruction set of computer is called RISC. One advantage of RISC is that they can execute their instructions very fast because the instructions are so simple. Another more important advantage is that RISC chips require fewer transistors, makes them cheaper to design and produce. The system on chip (SOC) design of 64 bit RISC processor consist of ALU, Shifter, comparator, RAM Memory, Control Unit, Program counter. Top design approach is used to configure the design. The design is synthesized on Spartan -3E FPGA for 33 instructions. VHDL programming language is used to develop the RISC in Xilinx 14.2 ISE design suit and functional simulated on Modelsim 10.1 b software.

Four Stage Pipelined 16 bit RISC on Xilinx Spartan 3AN FPGA

This paper describes the design and implementation of a 16 bit 4 stage pipelined Reduced Instruction Set Computer (RISC) processor on a Xilinx Spartan 3AN Field programmable gate array (FPGA). The processor implements the Harvard memory architecture, so the instruction and data memory spaces are both physically and logically separate. The RISC processor architecture presented in this paper is designed by six units, they are instruction cache, instruction unit, decode unit, execute unit, data cache unit and register file unit. The processor has been described using Verilog HDL, simulated using ModelSim 6.5-SE simulator and synthesized using Xilinx ISE 11.1i.The proposed processor has been implemented and physically tested Xilinx FPGA Spartan 3AN development board, It uses ChipScope Pro 9.2i embedded logic analyzer to monitor any or all of the signals in the design.

PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing) in the CPU/DSP (Digital Signal Processor) unit of OR1200 (Open Reduced Instruction Set Computer (RISC) 1200) using Gene Expression Programming (GEP) an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i) HPRC_Gene_Start ii) HPRC_Gene_End. A Verilog HDL(Hardware Description language) functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm

This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335Mbps and 176Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.

An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion

A self-timed subthreshold processor was developed in 65-nm complimentary metal-oxide-semiconductor process. This four-stage reduced instruction set computer processor synchronously operates with the memory read completion signal produced in 8.5-kb instruction and 2-kb data memories of subthreshold 10T static random-access memory. Measurement results show that the processor correctly functions from 0.56 to 0.36 V with a self-timed clock and achieves minimum energy per cycle of 3.47 pJ/cycle at 0.46-V supply voltage with 1.76-MHz average frequency. Compared with conventional synchronous operation with guardbanding, the proposed self-timed operation reduces the execution time of SHA-1 by 82% at 0.4-V supply voltage and saves energy by 40% to attain 1-MHz operation.

Massive video-surveillance parallelization on the Cell Broadband Engine processor

The Cell Broadband Engine® (Cell/B.E.®) is a multicore processor with a PowerPC® processor element (PPE) and eight synergistic processor elements (SPEs). The Cell/B.E. architecture is designed to improve upon conventional processors in terms of memory latency, bandwidth, and power consumption. In this paper, we discuss the parallelization, implementation, and performance of a video-surveillance application on the Cell/B.E. We report the video-surveillance application performance measured on a computer with one Cell/B.E. processor and with varying numbers of SPEs enabled. These results were compared with the results obtained on the single PPE of the Cell/B.E. with all eight SPEs disabled. The results indicate that our video-surveillance application performs approximately 25 times faster on the eight-SPE-core Cell/B.E. than modern reduced instruction set computer processors by processing input data from eight separate surveillance-video streams in parallel.

Enhancing the Performance of Symmetric-Key Cryptography via Instruction Set Extensions

In this paper, instruction set extensions for a reduced instruction set computer processor are presented to improve the software performance of the data encryption standard (DES), the triple DES, the international data encryption algorithm (IDEA), and the advanced encryption standard (AES) algorithms. The most computationally intensive operations of each algorithm are off-loaded to a set of newly defined instructions. The additional hardware required to support these instructions is integrated into the processor's data path. For each of the targeted algorithms, comparisons are presented between traditional software implementations and new implementations that take advantage of the extended instruction set architecture. Results show that the utilization of the proposed instructions significantly reduces program code size, and improves encryption and decryption throughput. Moreover, the additional hardware resources required to support the instruction set extensions increase the total area of the processor by less than 65%. Finally, it will be shown that the throughputs for triple DES, IDEA, and AES are approximately the same when accelerated via instruction set extensions. This allows for seamless and transparent algorithm agility as one algorithm may be easily replaced by another algorithm with minimal performance degradation.

Systematic Software-Based Self-Test for Pipelined Processors

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

MMV: A Metamodeling Based Microprocessor Validation Environment

With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges. The systematic validation approach starts with defining the correct behaviors of the hardware and software components and their interactions. This requires new modeling paradigms that support multiple levels of abstraction. Mutual consistency of models at adjacent levels of abstraction is crucial for manual refinement of models from the full chip level to production register transfer level, which is likely to remain the dominant design methodology of complex microprocessors in the near future. In this paper, we present microprocessor modeling and validation environment (MMV), a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage, and test generation tools. We illustrate the functionalities in MMV by modeling a 32-bit reduced instruction set computer processor at the system, instruction set architecture, and microarchitecture levels. We show by examples how consistency across levels is enforced during modeling and also how to generate constraints for automatic test generation.

The New Fault Tolerant Onboard Computer for Microsatellite Missions

This paper describes an onboard computer with dual processing modules. Each processing module is composed of 32 bit ARM reduced instruction set computer processor and other commercial-off-the-shelf devices. A set of fault handling mechanisms is implemented in the computer system, which enables the system to tolerate a single fault. The onboard software is organized around a set of processes that communicate among each other through a routing process. Meeting an extremely tight set of constraints that include mass, volume, power consumption and space environmental conditions, the fault-tolerant onboard computer has excellent data processing capability that can meet the erquirements of micro-satellite missions.

06/00941 Theoretical expression of rate of rise of recovery voltage across a circuit breaker connected with fault current limiter: Calixte, E. et al. Electric Power Systems Research, 2005, 75, (1), 1–8.

This paper describes an onboard computer with dual processing modules. Each processing module is composed of 32 bit ARM reduced instruction set computer processor and other commercial-off-the-shelf devices. A set of fault handling mechanisms is implemented in the computer system, which enables the system to tolerate a single fault. The onboard software is organized around a set of processes that communicate among each other through a routing process. Meeting an extremely tight set of constraints that include mass, volume, power consumption and space environmental conditions, the fault-tolerant onboard computer has excellent data processing capability that can meet the erquirements of micro-satellite missions.

Energy optimization of multilevel cache architectures for RISC and CISC processors

In this paper, we present the characterization and design of energy-efficient, on chip cache memories. The characterization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To optimize performance and power in a processor's cache, a multidivided module (MDM) cache architecture is proposed to conserve energy in the bit array as well as the memory peripheral circuits. Compared to a conventional, nondivided, 16-kB cache, the latency and power of the MDM cache are reduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cache architecture, the energy efficiency of the complete memory hierarchy is analyzed with respect to cache parameters in a multilevel processor cache design. This analysis was conducted by executing the SPECint92 benchmark programs with the miss ratios for reduced instruction set computer (RISC) and complex instruction set computer (CISC) machines.

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-/spl mu/m CMOS with double-well and triple-metal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.

Uniformity Middle Ware for Photo-Printing

An effective and flexible photo-printing controller for D2T2 (Dye Diffusion Thermal Transfer) and photo inkjet is proposed. The objectives of the present work are to develop the controller architecture using RISC (Reduced Instruction Set Computer) processor and its middle-ware especially used for uniformity correction. In present architecture, the middle-ware provides functional compatibility in the middle layer between hardware and application software.

Optimization of particle-in-cell codes on reduced instruction set computer processors

General strategies are developed to optimize particle‐cell codes written in Fortran for reduced instruction set computer processors which are commonly used on massively parallel computers. These strategies include data reorganization to improve cache utilization and code reorganization to improve efficiency of arithmetic pipelines. Results show performance improvements of 1.4–3.4 times can be achieved. © 1996 American Institute of Physics.

CISC, RISC and DSP processors in real-time signal processing and control

This paper presents an investigation into the performance evaluation of advanced complex instruction set computer (CISC) processors, reduced instruction set computer (RISC) processors and digital signal processing (DSP) devices in the real-time implementation of signal processing and control algorithms. The algorithms considered are of varying degree of regularity relative to one another. These include a fast Fourier transform algorithm, a second-order correlation algorithm, two adaptive filtering algorithms, a simulation algorithm of a flexible manipulator system and simulation, identification and active vibration control algorithms of a flexible beam system. The algorithms are implemented on an 80486DX2 CISC processor, an 80386DX CISC processor, a SPARC TMS390S10 RISC processor, a T805 RISC processor, an 80i860 RISC processor and a TMS320C40 DSP device. The hardware and software resources and capabilities of the processors and the characteristics of the algorithms are discussed to provide a matching between the algorithms and the architectures. Finally, a comparison of the results of the implementations, on the basis of real-time computation performance, is made and discussed.

Operating experience with a VMEbus multiprocessor system for data acquisition and reduction in nuclear physics

Summary form only given, as follows. A multiprocessor system based on commercially available VMEbus components has been developed for the acquisition and reduction of event-mode data in nuclear physics experiments. The system contains seven 68000 CPUs and 14 Mbyte of memory. A minimal operating system handles data transfer and task allocation, and a compiler for a specially designed event analysis language produces code for the processors. The system has been in operation for four years at the University of Pennsylvania Tandem Accelerator Laboratory. Computation rates over three times that of a MicroVAX II have been achieved at a fraction of the cost. The use of WORM optical disks for event recording allows the processing of gigabyte data sets without operator intervention. A more powerful system is being planned which will make use of recently developed RISC (reduced instruction set computer) processors to obtain an order of magnitude increase in computing power per node.

Macintosh Workstations

Reduced Instruction Set Computer (RISC) processors represent a different way to design a CPU for a workstation. They are not magical elixirs to supercharge a personal computer into a mainframe; rather, they are simply a different approach to handling information. RISC design has already affected the architecture of more traditional CISC (Complex Instruction Set Computer) processors and will continue to do so well into the next decade. Given the wealth of software written for CISC processors and the pau‐city of RISC shaped applications, combined with the usual lag in software development behind any hardware breakthrough, a full‐fledged RISC library workstation may not appear for some time. Nevertheless RISC has earned a great deal of attention since its practical birth at IBM in 1976 by John Cocke and its pursuit in academic circles at Stanford and the University of California, Berkeley in the early 1980s. Bom from the simple idea of devising a way to complete a computer instruction in a single cycle of a processor, RISC architecture has been called the de facto standard of the next decade for workstations by some and a mere fad by others. Will these chips replace CISC processors entirely? Will they have an impact on library workstations? And will they ever appear in one form or another in the Macintosh? With RISC processors available from MIPS Computer Systems, Motorola, and Sun, and RISC‐based computers produced by Apollo, Sun, Everex, Hewlett‐Packard, and others, RISC is certainly a harbinger of the future of processors in workstations. The market for RISC‐based worksta‐tions is heating up as some manufacturers — Sun, DEC, Data General to mention a few — battle for customers by lowering prices and raising performance.

A 20 K CMOS array with 200-ps gate delay

A 20 K NAND2 equivalent CMOS gate array prototype with 0.5- mu m channel length FETs is described. The 7.5*7.5-mm chip is designed for high performance with 200-ps gate delay. Large macros such as a 32-b RISC (reduced instruction-set computer) processor and 128*8 SRAM (static random-access memory) have been implemented with automatic placement and wiring tools. Their respective predicted performances of 17-ns cycle and 6.1-ns access time have been verified. This confirms that the speed of complex functions in half-micrometer-channel-length CMOS technology is getting close to the speed achieved by current bipolar hardware.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Making RISC respectable — the Motorola 88000

The reduced instruction set computer (RISC) was initially regarded with considerable scepticism, but Motorola&apos;s launch of a new RISC processor represents a significant advance in the acceptance of the RISC design philosophy