Reduce Chip Area Research Articles

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs

This paper introduces memristor-based operational amplifiers (OpAmps) in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop OpAmps. An inverting OpAmp, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area.

Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm

Digital signal processing (DSP) algorithms are actually nothing but sum of product. So, they are computationally intensive. All the mathematical tasks related to DSP algorithm are based on multiplication and addition. So, the implementations of DSP algorithms-based applications extensively require multiplier and adder. Due to extensive use of multiplication and addition operation, speed up cannot be achieved. Designing the high-performance adder and multiplier are primary objective for implementing high performance signal processing applications. This hindrance can be removed by Multiply-Accumulate Unit (MAC). The special feature of a MAC unit is its ability to perform single cycle multiplication and addition operation.The performance of MAC Unit can be improved by using non-binary number system. Ternary value logic (TVL) has the ability to offer several advantages over conventional binary number system like reduce chip area, reduce overall delay. TVL can switch between three levels, such levels denoted by 0, 1, 2. As Residue Number Systems (RNS) can perform carry arithmetic operations, high performance adder can be implemented using RNS in TVL domain (TRNS). Partial product free multiplication can be implemented by using Double Base Number System in TVL domain (DBTNS). Double Base Ternary Number System (DBTNS) multiplier can perform better than conventional TVL multiplier. A MAC unit is used to perform the multiplication and accumulator operations together to avoid unnecessary overhead on the processor in terms of processing time and the on-chip memory requirements. Keeping in view of these issues, a new architecture is proposed for implementing high performance MAC unit for DSP applications. In this paper, a new approach of designing MAC unit is instigated using DBTNS multiplier and TRNS adder. A major bottleneck of implementing this architecture is the complexity involved in converting TVL to DBTNS in initial stage and converting TRNS to TVL in final stage. The performance of Ternary Residue Number Systems (TRNS) system depends on selection of moduli because selection of moduli is not properly maintained then it will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.

Reliability of Novel Ceramic Encapsulation Materials for Electronic Packaging

Abstract Enhancements on power electronic systems with reduced chip area and miniaturized passive components are subject of several research activities in academics and industry. To realize such future electronic devices, it is necessary to incorporate wide bandgap semiconductor technology such as silicon carbide and gallium nitride operating at higher temperatures. Therefore, the development of novel materials with high thermal conductivities and stability, withstanding harsh environments up to 300°C is of major interest. Especially, polymeric encapsulation materials have to be improved because of common degradation effects above 175°C. Ceramic (nonpolymeric) materials with thermal conductivities above 5 W/(m·K) already illustrated promising results for the encapsulation of power electronics. The present work illustrates recent developments and improvements on novel ceramic encapsulation materials, which finally avoid critical interactions with the chip surface. Furthermore, advances in reliability will be discussed in terms of passed high-temperature reverse bias and humidity tests correlated with relevant material properties.

A fully integrated 4-channel beamformer based on TTD phased array in 0.18μm CMOS

A fully integrated 4-channel beamformer based on TTD phased array is proposed in this paper. This architecture is especially suitable for MIMO systems which can increase throughput by improving multiplexing gain. A path-sharing true time delay (TTD) unit by using analog CMOS filter circuits is presented to realize flat time delay over 0.35–1 GHz. Compared to traditional MIMO architectures, highly multiplexed TTD reduces chip area and power consumption. The proposed beamformer can provide maximum scan angle of up to ±45°for four antennas with 10.5 cm spacing. The measurement results show that maximum delay is almost consistent with simulated results. Input signals from the same direction which reach different antennas, are delayed a different fixed time difference through different TTD units and have same phase at the output, realizing signal enhancement. The whole beamformer chip consumes 130 mA from a 1.8 V DC power supply, and has a total chip area of 4.65 mm × 4.30 mm.

A 6-bit CMOS Active Phase Shifter for <italic>Ku</italic>-Band Phased Arrays

A 6-bit high-accuracy active phase shifter is developed in 0.13- $\mu \text{m}$ CMOS technology for Ku -band phased arrays. Improved transformer balun with wriggly stub is applied to split the single input to differential and achieve high balance with reduced chip area. Two-stage polyphase filter (PPF) generates broadband I/Q signals with high accuracy. A main digital-to-analog convertor (DAC) controls the I/Q amplitude to achieve 6-bit phase resolution, while an auxiliary DAC compensates the amplitude/phase error introduced by balun and PPF. Consequently, high resolution along with low phase/gain error can be achieved. The phase shifter shows measured rms phase error of $0.75 \times 0.32$ mm2 excluding pads.

Reliability of Novel Ceramic Encapsulation Materials for Electronic Packaging

Abstract Enhancements on power electronic systems with reduced chip area and miniaturized passive components are subject of several research activities in academics and industry. To realize such future electronic devices, it is necessary to incorporate wide bandgap semiconductor technology such as silicon carbide and gallium nitride operating at higher temperatures. Therefore, the development of novel materials with high thermal conductivities and stability, withstanding harsh environments up to 300°C is of major interest. Especially, polymeric encapsulation materials have to be improved because of common degradation effects above 175°C. Ceramic (nonpolymeric) materials with thermal conductivities above 5 W/(m·K) already illustrated promising results for the encapsulation of power electronics. The present work illustrates recent developments and improvements on novel ceramic encapsulation materials, which finally avoid critical interactions with the chip surface. Furthermore, advances in reliability will be discussed in terms of passed high-temperature reverse bias and humidity tests correlated with relevant material properties.

DPL-based novel Binary-to-ternary converter on CMOS technology

Encoding radix-2 data in radix-3 has the potential to allow faster computation with reduced power dissipation, reduced chip area and reduced interconnect overhead. Use of ternary encoding has the potential to minimize hot-spot generation and bring down fabrication costs due to reduced complexity. Efficient binary-to-ternary conversion is needed to attain these benefits in today's binary-dominated digital world. This paper presents a novel strategy to convert from a 2-valued binary input to a 3-valued ternary output. The proposed converter operates in 4 steps: (I) Synchronous complementary input generation, (II) Binary to unary conversion, (III) Unary to ternary interfacing, and (IV) Ternary output generation. A design using double pass-transistor logic delay equalized through coarse and fine-tuning is presented. Ternary values are encoded using 0, 0.9 and 1.8 V to represent ternary digit (trit) values of 0, 1 and 2. The proposed converter design has been validated using T-Spice transient-response simulation on TSMC 0.18 µm SPDM CMOS technology at 25 °C on Tanner EDA V.13. The worst-case response of the proposed design was identified using corner analysis with typical, slow and fast PVT variation.

A Concurrent Dual-Band and Dual-Mode Frequency Synthesizer for Radar Systems

A simultaneous dual-band dual-waveform frequency synthesizer suitable for radar applications is presented. By using a K-band integer-N phase-locked loop (PLL) in conjunction with a W-band frequency modulation loop, a K-band sinusoidal carrier and W-band frequency-modulated continuous-wave frequency chirp can be generated concurrently. Due to the single PLL architecture for dual-band signal generation, additional loop filter, phase frequency detector, and dividers are no longer required for reduced chip area and power consumption. Fabricated in a 90-nm CMOS process, the proposed circuit occupies an area of 1.26 mm $\times1.675$ mm and consumes a dc power of 67 mW from a supply voltage of 1.2 V.

Voltage Mode Multiple Valued Analog to Quaternary Mapping

Most of the digital processing is performed in the binary domain. With the increasing integration, chip area became an important resource to improve transistor density and energy efficiency. An alternative to reduce chip area is to increase the representation up to base B, domain D: (0, 1, 2,..., B - 1) known as Multiple-Valued Logic (MVL) to decrease chip wirings due to the fact that approximately 70% chip area is devoted to the interconnections. For the digital processing of analog signals an Analog to Digital Mapping is needed. This proposal is a mapping and not a complete analog to digital converter (ADC) due to the fact that there are not any circuits to correct errors, for example: linearity, bits synchronization, etc. This work presents a voltage mode multiple valued analog to quaternary mapping architecture for two digits utilizing the chosen universal set of MVL operators presented in the literature for quaternary base B=4:eAND1, eAND2, eAND3, Successor, and Maximum that allows to design any MVL digital circuit. Simulations on Cadence Tools for the AMS CMOS 0,35 μm technology will be presented to demonstrate concepts and circuit feasibility and functionality, showing correct behavior with respect to the specification and compatibility with the chosen universal set of gates.

Reliability improved, high performance FIR filter design using new computation sharing multiplier: suitable for signal processing applications

The finite impulse response (FIR) filter are class of digital filter are extensively used in signal processing and in communication system applications such as noise reduction, echo cancellation and image enhancement etc. Designing a FIR filter with less computation time, low power and by using minimum hardware playing a major role in overall performance of the application where FIR filter is involved. The research work presented in this paper has been carried out to fulfil the above said aim. In this research work, 16 tap FIR filter has been implemented using newly proposed floating point Computation Sharing High Speed Multiplier (CSHM). Since in FIR filter, floating point multiplication is involved in each and every tap of filter operation, bringing the floating point multiplication architecture with less computation time, low power and with minimum hardware will automatically improve the performance of FIR filter. The newly proposed computation sharing multiplier differs from existing computation sharing multiplier with respect to fixed alphabet entries in a precomputer unit and efficient computation of distributed arithmetic based vector scalar product. Front end and backend design of a 16 tap FIR filter using newly proposed CSHM and existing CSHM has been carried out using Cadence® nclaunch®, RC® and Encounter® tool with tsmc 180 nm technology library. Comparison result of 16 tap FIR filter shows that 18% reduction in chip power, 13% reduction in chip area and 26% reduction in cell count has been achieved with newly proposed floating point CSHM compare to 16 tap FIR filter designed with existing CHSM. This research work also proposes efficient automation algorithms which improve the design for manufacturability (DFM) of a post layout of a 16 tap FIR filter designed which will improve the reliability of integrated circuits. There are many DFM guidelines have to be followed during layout design. In this research work, the automation algorithm has been proposed for one of the DFM guideline called VIA-Redundancy. The aim of this automation algorithm is to replacing single VIA with double VIA wherever possible. In case of “L” transition routing, single contacts can be very sensitive to resistivity spread and defect. The probability to have too resistive transition will be very much minimized by inserting a new contact which reduces electro-migration effect. Through this automation algorithm redundancy percentage of all the VIA’s of FIR filter designed has been increased without compromising chip area, power and computation time much. The specialty of this automated algorithm is that this can be used to any design which has been implemented on the same platform and technology node. The proposed algorithm automated through Tcl 8.6, UNIX platform.

Compensator-Free Mixed-Ripple Adaptive On-Time Controlled Boost Converter

A mixed-ripple adaptive on-time controlled boost converter is proposed. With the proposed control method, the compensator network is no longer required. Hence, the chip area and cost can be reduced, and a satisfied load regulation still can be achieved. Besides, a novel on-time generator is proposed to fix the switching frequency in continuous conduction mode (CCM). Moreover, a differential difference comparator is proposed to simplify the circuits and further reduce chip area. Furthermore, with the proposed control, the converter is capable of smoothly switching between discontinuous conduction mode and CCM, depending on the loading condition. The proposed boost converter was implemented by using a 0.18- $\mu \text{m}$ 1P6M mixed-signal process, and the chip area is 0.88 mm2. The input voltage may range from 0.8 to 1.4 V, the output voltage is set to 1.8 V, and the measured peak efficiency is 92.4%.

On-chip calibration and control of optical phased arrays.

Optical phased arrays (OPAs) are important as they allow beam steering and scanning with no moving parts. As their channel count increases, the complexity of control and calibration becomes challenging. We propose an architecture and algorithm that provide rapid on-chip calibration and are scalable to arbitrary channel counts with significantly reduced chip area and reduced overall complexity compared to previously proposed approaches. The optimized phase shifter tuning algorithm - Deterministic Stochastic Gradient Descent (DSGD) - rapidly converges to the optimal state speeding up the digital-to-analog converter based control of large channel count OPAs.

Design of Low-Cost Transimpedance Amplifier for Optical Receiver

The transimpedance amplifier (TIA) is the most favorable and efficient choice for the front-end preamplifier in optical fiber communication systems. High gain and low input noise to amplify weak and susceptible input signals are the two major advantages of TIAs. Moreover, to realize a low-cost solution, a TIA should be implemented in a complementary metal-oxide semiconductor (CMOS) process and should occupy a small area. This paper presents a low-cost TIA for optical receivers in a 180-nm CMOS process. The proposed TIA combines both open-loop and closed-loop topologies. A capacitance isolation method is used for noise and bandwidth optimization. Finally, capacitive peaking is used for bandwidth enhancement. Moreover, the proposed TIA is designed without using any inductors for bandwidth enhancement as well as for reducing chip area. Simulation results show that the proposed TIA works up to a frequency of 2.2 GHz with a transimpedance gain of 54.4 dBΩ. The TIA consumes only 19.7 mW with a supply voltage of 1.8 V, and the active area of the proposed circuit is only 0.003 mm2.

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control

The Harmonized Parabolic Synthesis methodology is a further development of the Parabolic Synthesis methodology for approximation of unary functions such as trigonometric functions, logarithms and the square root with moderate accuracy for ASIC implementation. These functions are extensively used in computer graphics, communication systems and many other application areas. For these high-speed applications, software solutions are not sufficient, and a hardware implementation is therefore needed. The Harmonized Parabolic Synthesis methodology has two outstanding advantages: it is parallel, thus reducing the execution time, and it is based on low complexity operations, thus being simple to implement in hardware. A difference compared to other approximation methodologies is that it is a multiplicative, and not additive, methodology. Compared to the Parabolic Synthesis methodologies it is possible to significantly enhance the performance in terms of reducing chip area, computation delay and power consumption. Furthermore, it increases the possibility to tailor the characteristics of the error, improving conditions for subsequent calculations. To evaluate the methodology, the fractional part of the logarithm is implemented and its performance is compared to the Parabolic Synthesis methodology. The comparison is made with 15-bit resolution. The design implemented using the proposed methodology performs 3× better than the Parabolic Synthesis implementation in terms of throughput, while consuming 90% less energy. The chip area is 70% smaller than for the Parabolic Synthesis methodology. In summary, the new technology further increases the advantages of Parabolic Synthesis.

MOS-only complex filter design for dual-band GNSS receivers

In this paper, the use of MOS-only active filters in the implementation of area-effective low-IF image reject filters is discussed. For this purpose, complex filter design procedure is considered regarding MOS-only filter realization techniques and a new second-order filter topology which favors filter’s area-effective implementation is proposed. Owing to the presented approach, a new complex image-reject filter with reduced chip area, which can be used in dual-band GNSS receivers, is obtained. Issues related to IQ imbalance are briefly discussed and a calibration imbalance circuit is proposed. By virtue of the current-mode design technique, the IQ imbalance circuit is embedded with the complex filter, simplifying the system topology. In order to illustrate the feasibility of the filter, post-layout simulation results of a fourth-order Butterworth-type image reject filter designed for dual-band GNSS receivers are provided using SPECTRE simulation tool in CADENCE design environment.

A High-Performance Piezoelectric Vibration Sensor

We are reporting on the design, fabrication, and characterization of wideband, piezoelectric vibration microsensors. Prototypes were fabricated in a commercial foundry process. The entire thickness of the handle wafer was employed to carve the proof-mass of the device, leading to high sensitivity at a reduced chip area. A thin layer of aluminum nitride was used for sensing the displacements of the proof-mass. A continuous membrane was employed for the device structure in order to push undesired modes to high frequencies. Sensors with different geometries were designed and fabricated. Analytic and finite element analyses were conducted to study device response. A lump element model was developed for the piezoelectric vibration sensor and used for the noise modeling of the complete sensor system. Various performance metrics for the devices were characterized experimentally. Fabricated prototypes exhibited sensitivities as high as 350 mV/g with first resonant frequencies of more than 10 kHz. These devices are particularly suited for emerging applications in high-frequency vibration sensing.

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

Design of Wideband LNA Employing Cascaded Complimentary Common Gate and Common Source Stages

A wideband low noise amplifier (LNA) is presented, which composes of cascaded complimentary common gate (CCG) stage and common source (CS) stages. Based on the current reusing technique, the CCG stage saves dc power and reduces chip area by replacing two inductors with one transformer. The source-degenerated CS stage helps form a frequency-dependent load for the CCG stage. With a load reusing technique, this load can be transformed to the input and helps achieve simultaneous wideband gain, wideband input matching, and flat noise figure (NF) over the desired band. The proposed LNA shows the measured 3-dB bandwidth from 7.6 to 29 GHz, the maximum power gain of 10.7 dB, and the NF from 4.5 to 5.6 dB. The power consumption is 12.1 mW with 1-V supply voltage and the chip occupies an area of 0.3 mm2 in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS process.

Low Overhead Architectures for OMP Compressive Sensing Reconstruction Algorithm

Orthogonal Matching Pursuit (OMP) is an important compressive sensing (CS) recovery and sparsity inducing algorithm, which has potential in various emerging applications ranging from wearable and mobile computing to real-time analytics processing on servers. Thus application aware OMP algorithm implementation is important. In this paper, we propose two different modifications to OMP algorithm named Thresholding technique for OMP (tOMP) and Gradient Descent OMP (GDOMP) to reduce hardware complexity of OMP algorithm. tOMP modifies identification stage of OMP algorithm to reduce reconstruction time and GDOMP modifies residual update phase to reduce chip area. To demonstrate reconstruction efficiency of proposed OMP modifications, we compare signal-to-reconstruction error rate (SRER), signal-to-noise ratio (PSNR), and Structural Similarity index (SSIM) of previously proposed matching pursuit algorithms such as Subspace Pursuit (SP), Look Ahead OMP (LAOMP), and OMP, with tOMP, and GDOMP. We implemented reconfigurable, parallel, and pipelined architectures for three algorithms including OMP, tOMP, and GDOMP which can reconstruct different data vector sizes ranging from 128 to 1024, on 65 nm CMOS technology operating at 1 V supply voltage. The post place and route analysis on area, power, and latency show that, tOMP requires 33% less reconstruction time, and GDOMP consumes 44% less chip area when compared to OMP ASIC implementation. Compared to previously published work, the proposed architectures achieve 2.1 times improvement in Area-Delay product (ADP) and consume 40% less energy.