Reduced Gate Leakage Research Articles

HfO2‐insulated gate N‐polar GaN HEMTs with high breakdown voltage

AbstractIn this paper, we present the first demonstration of a HfO2‐insulated gate N‐polar GaN inverted high‐electron‐mobility transistor (iHEMT). HfO2‐insulated gate devices showed an order of magnitude improvement in reverse‐bias gate leakage current as compared to reference Schottky devices. With the reduced gate leakage current, the insulated gate iHEMTs were able to simultaneously demonstrate breakdown voltages in excess of 130 V and maximum current density of 0.87 A/mm. Pulsed I–V gate‐lag measurements were performed to investigate the drain current transient behavior of these devices.

(Invited) Impact of Stacked AlON/SiO2 Gate Dielectrics for SiC Power Devices

We propose the use of an aluminum oxynitride (AlON) gate insulator for SiC-based MOS power devices. Although direct deposition of AlON on 4H-SiC substrate causes electrical degradation, the fabricated MOS capacitor with AlON/SiO2 stacked gate dielectric shows no flatband voltage (VFB) shift and negligible capacitance-voltage (C-V) hysteresis. Owing to the high dielectric constant of AlON, as compared to single SiO2 insulator, significant gate leakage reduction was achieved even at high-temperatures, especially in high electric field condition. Moreover, in order to improve electrical properties of thermally grown SiO2/SiC interfaces, the impact of a combination treatment of nitrogen plasma exposure and forming gas annealing (FGA) was investigated. We found that channel mobility enhancement of SiC-MOSFETs was consistent with the reduction in interface state density (Dit) depending on the process conditions of the combination treatment, and obtained 50% mobility enhancement, while maintaining low gate leakage current.

Si/SiGe quantum dot with superconducting single-electron transistor charge sensor

We report a robust process for fabrication of surface-gated Si/SiGe quantum dots (QDs) with an integrated superconducting single-electron transistor (SSET) charge sensor. A combination of a deep mesa etch and AlOx backfill is used to reduce gate leakage. After the leakage current is suppressed, Coulomb oscillations of the QD and the current-voltage characteristics of the SSET are observed at a temperature of 0.3 K. Coupling of the SSET to the QD is confirmed by using the SSET to perform sensing of the QD charge state.

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Negative bias temperature instability (NBTI) in pMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in nMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guard banding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.

Intrinsic Reliability Improvement in Biaxially Strained SiGe p-MOSFETs

In this letter we not only show improvement in the performance but also in the reliability of 30nm thick biaxially strained SiGe (20%Ge) channel on Si p-MOSFETs. Compared to Si channel, strained SiGe channel allows larger hole mobility ({\mu}h) in the transport direction and alleviates charge flow towards the gate oxide. {\mu}h enhancement by 40% in SiGe and 100% in Si-cap SiGe is observed compared to the Si hole universal mobility. A ~40% reduction in NBTI degradation, gate leakage and flicker noise (1/f) is observed which is attributed to a 4% increase in the hole-oxide barrier height ({\phi}) in SiGe. Similar field acceleration factor ({\Gamma}) for threshold voltage shift ({\Delta}VT) and increase in noise ({\Delta}SVG) in Si and SiGe suggests identical degradation mechanisms.

Chemically Cross-Linked Thin Poly(vinylidene fluoride-co-trifluoroethylene)Films for Nonvolatile Ferroelectric Polymer Memory

Both chemically and electrically robust ferroelectric poly(vinylidene fluoride-co-trifluoro ethylene) (PVDF-TrFE) films were developed by spin-coating and subsequent thermal annealing with the thermal cross-linking agent 2,4,4-trimethyl-1,6-hexanediamine (THDA). Well-defined ferroelectric β crystalline domains were developed with THDA up to approximately 50 wt %, with respect to polymer concentration, resulting in characteristic ferroelectric hysteresis polarization-voltage loops in metal/cross-linked ferroelectric layer/metal capacitors with remnant polarization of approximately 4 μC/cm(2). Our chemically networked film allowed for facile stacking of a solution-processable organic semiconductor on top of the film, leading to a bottom-gate ferroelectric field effect transistor (FeFET). A low-voltage operating FeFET was realized with a networked PVDF-TrFE film, which had significantly reduced gate leakage current between the drain and gate electrodes. A solution-processed single crystalline tri-isopropylsilylethynyl pentacene FeFET with a chemically cross-linked PVDF-TrFE film showed reliable I-V hysteresis with source-drain ON/OFF current bistablility of 1 × 10(3) at a sweeping gate voltage of ±20 V. Furthermore, both thermal micro/nanoimprinting and transfer printing techniques were conveniently combined for micro/nanopatterning of chemically resistant cross-linked PVDF-TrFE films.

Gate leakage reduction through the use of a gate-to-source/drain non-overlapped metal–oxide–semiconductor field-effect transistor structure

In this paper, a novel, nanoscale, metal–oxide–semiconductor field-effect transistor (MOSFET) with gate-to-source/drain non-overlapped and high- k spacer structure has been demonstrated to reduce gate leakage current for the first time. The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. The fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended source/drain region. It is found that the optimal gate-to-source/drain non-overlapped and high- k spacer structure reduces the gate leakage current to a great extent compared with an overlapped structure. Further, the proposed structure has an improved off-current, sub-threshold slope, and drain-induced barrier-lowering characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Nonvolatile Polymer Memory with Nanoconfinement of Ferroelectric Crystals

We demonstrate significantly improved performance of a nonvolatile polymeric ferroelectric field effect transistor (FeFET) memory using nanoscopic confinement of poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) within self-assembled organosilicate (OS) lamellae. Periodic OS lamellae with 30 nm in width and 50 nm in periodicity were templated using block copolymer self-assembly. Confined crystallization of PVDF-TrFE not only significantly reduces gate leakage current but also facilitates ferroelectric polarization switching. These benefits are due to the elimination of structural defects and the development of an effective PVDF-TrFE crystal orientation through nanoconfinement. A bottom gate FeFET fabricated using a single-crystalline triisopropylsilylethynyl pentacene channel and PVDF-TrFE/OS hybrid gate insulator shows characteristic source-drain current hysteresis that is fully saturated at a programming voltage of ±8 V with an ON/OFF current ratio and a data retention time of approximately 10(2) and 2 h, respectively.

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

Methodology of ALD HfO2 High-κ Gate Dielectric Optimization by Cyclic Depositions and Anneals

This paper presents the optimization of HfO2 high-κ gate dielectrics by utilizing cyclic depositions and anneals during atomic layer deposition (ALD). An order of magnitude reduction in gate leakage is obtained by tuning the anneal temperature, duration and sequence in the ALD. The films are also seen to have three to four times reduction in carbon content. These optimized films are moreover observed to be densified without compromising equivalent oxide thickness (EOT), carrier mobility and threshold voltage. Further electrical characterization supports that there is a suppression of trap assisted tunneling with the optimized ALD process by revealing a stronger temperature dependence on the annealed samples as opposed to the conventional ALD process.

A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials

Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing total leakage dissipations with additional load capacitances using SPICE simulations. Compared to N-type clocked adiabatic logic (N-CAL) circuits, the total power and leakage power dissipation of P-type CAL circuits are reduced greatly.

Stress Liner Effects for 32-nm SOI MOSFETs With HKMG

Strain effects from stress liners on silicon-on-insulator MOSFETs with high-k dielectric and metal gate (HKMG) are reported. By thoroughly evaluating their impact on drive current, mobility, and threshold voltage, the intrinsic performance gain of stress liners is quantified at the 32-nm node with mobility enhancement identified as the major source. It is also experimentally demonstrated that advantageous stress liners can reduce gate leakage currents for MOSFETs with HKMG.

Dependence of Electrical Properties of InAlN/GaN and InAlN/AlGaN/GaN Heterostructures FETs on the AlN Interlayer Thickness

We investigated the influence of the thickness of the AlN interlayer for InAlN/GaN and InAlN/AlGaN/GaN heterostructures. The AlN thickness strongly affects the surface morphology and electron mobility of the InAlN/GaN structures. The rms roughness of the surface increases from 0.35 to 1.2nm with increasing AlN thickness from 0 to 1.5nm. Large pits are generated when the AlN is thicker than 1nm. The highest electron mobility of 1470cm2/V·s is obtained for a 0.75-nm-thick AlN interlayer. The mobility, however, becomes lower with increasing deviation from 0.75nm. It is only 200cm2/V·s for the 0-nm thick AlN. Inserting AlGaN between AlN and InAlN suppresses the influence of the AlN interlayer thickness. A smooth surface with rms roughness of 0.35nm is obtained for all samples with 0-1.5-nm-thick AlN. The electron mobility ranges from 1000 to 1690cm2/V·s. The variation is smaller than that for InAlN/GaN. We fabricated field effect transistors (FETs) with gate length of 2µm. The electron mobility in the access region affects the transconductance (gm) of FETs. As a results, the influence of the AlN thickness for InAlN/GaN FETs is larger than that for InAlN/AlGaN/GaN FETs, which reduces gate leakage current. The transconductance varies from 93 to 235mS/mm for InAlN/GaN FETs. In contrast, it varies from 180 to 230mS/mm for InAlN/AlGaN/GaN FETs. These results indicate that the InAlN/AlGaN/GaN heterostructures could lead to the development of GaN-based FETs.

Tunneling current in gate dielectric stack in sub‐45 nanometer CMOS devices

AbstractDirect tunneling current through dual layer SiO2/high‐K dielectric structures are investigated for substrate injection. Correlation of dielectric constants and band offsets with respect to silicon has been taken into consideration in order to identify possible materials to construct these devices. The direct tunneling current in oxide/high‐K dielectric structures with equivalent oxide thickness (EOT) of 2.0 nm can be significantly lower than that through single layer oxides of the same thickness. Various structures and materials of high‐K stacks of interest have been examined and compared to access the reduction of gate current in these structures. It is estimated that HfO2/SiO2 dual stack structure can reduce gate leakage current by four orders of magnitude as compared with pure SiO2 layer of same EOT. The importance of interfacial layer in dual stack structure is high‐lighted for the reduction of gate leakage current. The present approach is capable of modeling high‐K stack structures consisting of multiple layers of different dielectrics (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 °C because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

Atomic Layer Deposition of High-k Oxides on InAlN/GaN-based Materials

We demonstrate the applicability of atomic layer deposition of Al2O3 and ZrO2 on InAlN/GaN-materials by means of Metal Oxide Semiconductor High Electron Mobility Transistors (MOS-HEMTs). We investigate the impact of various surface pre-treatment methods, as well as the impact of in-situ pre-treatment by ALD on the electrical characteristics to evaluate insulation quality and thermal stability of the gate oxide stack, threshold voltage and interface traps. We show that by using the right surface pre-treatment as well as by using an adapted ALD pulsing scheme, one can obtain clearly improved MOS-HEMT performance concerning reduced gate leakage currents, suppressed current collapse effects, and increased drain currents

Thermal nitridation passivation dependent band offset and electrical properties of AlOxNy/GaAs gate stacks

Fermi level pinning attributed to oxides at the GaAs/high-k interface is a major obstacle to develop GaAs-based metal-oxide-semiconductor devices with high performance. In this letter, thermal nitridation treatment of GaAs surface prior to the high-k deposition is proposed to solve the issue of interface pinning. Results have confirmed that nitridation passivation effectively suppresses the oxides formation and leads to a shift in the Fermi level toward the conduction band minimum on the GaAs surface, which increases the conduction band offset at the GaAs/AlOxNy interface, followed by a saturated accumulation capacitance with reduced gate leakage current.

Impact of post-nitridation annealing on ultra-thin gate oxide performance

Decoupled-Plasma Nitridation (DPN) process with high level of nitrogen incorporation is widely used in the state-of-the-art technology, in order to reduce gate leakage current and boron penetration. However, due to the low temperature DPN process, the post-nitridation annealing treatment is required to improve the ultra-thin gate oxide integrity. In this paper, the effect of post-nitridation annealing on DPN ultra-thin gate oxide was investigated. The device performance and reliability were evaluated in three different post-nitridation annealing ambient (N 2/O 2, He, and NO).

The effects of hydroxyl-free polystyrene buffer layer on electrical performance of pentacene-based thin-film transistors with high-k oxide gate dielectric

We have investigated the effects of hydroxyl-free polystyrene (PS) as buffer layer on pentacene-based low-voltage organic thin-film transistors (OTFTs). The PS buffer layer is formed on the HfO 2 layer evaporated on Si substrate by spin-coating method prior to pentacene deposition, existence of which results in a dramatic increase of field effect mobility from 0.09 to 0.59 cm 2/Vs and negligible hysteresis. The improved mobility and hysteresis of the OTFTs can be attributed to the formation of smooth and nonpolar hydroxyl-free PS/HfO 2 gate dielectric surface. The PS insulator buffer layer can also effectively reduce gate leakage current by more than 70%. The results demonstrate that using appropriate polymer buffer layer is favorable to improve the performance of the OTFTs operating at low voltages with high mobility and good electrical stability.

MOSFET characteristics with poly-Si/HfAlON gate stacks using ultra-thin UV-ozone interfacial oxide

This paper conducts a comprehensive evaluation of the electrical characteristics of the poly-silicon gated n-channel metal–oxide–semiconductor field-effect-transistor (nMOSFET) with hafnium–aluminum-oxynitride (HfAlON) gate dielectric with interfacial ultraviolet-ozone (UV-O 3) oxide or chemical oxide. Interfacial UV-O 3 oxide exhibits well-controlled interfacial properties due to self-saturated growth and thick-oxide-comparable density, which is beneficial to suppress interfacial re-oxidation and reduces surface roughness. Compared with interfacial chemical oxide, the interfacial UV-O 3 oxide obviously improves both gate insulating and interface characteristics, including breakdown voltage increments, reduced gate leakage current, and as-deposited traps. In addition, the HfAlON gate stack with UV-O 3 interface oxide also shows encouraging nMOSFET device performances, with a small subthreshold swing, high electron mobility, saturation drain current, and negligible stress-induced trap generation. The results clearly suggest that the high-density interfacial UV-O 3 oxide possess a high potential to be integrated with further high-k dielectric applications.