Gate leakage reduction through the use of a gate-to-source/drain non-overlapped metal–oxide–semiconductor field-effect transistor structure

Abstract

In this paper, a novel, nanoscale, metal–oxide–semiconductor field-effect transistor (MOSFET) with gate-to-source/drain non-overlapped and high- k spacer structure has been demonstrated to reduce gate leakage current for the first time. The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. The fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended source/drain region. It is found that the optimal gate-to-source/drain non-overlapped and high- k spacer structure reduces the gate leakage current to a great extent compared with an overlapped structure. Further, the proposed structure has an improved off-current, sub-threshold slope, and drain-induced barrier-lowering characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.