Recovery Circuit Research Articles

Analysis of Mueller–Muller Clock and Data Recovery Circuits with a Linearized Model

With the development of high-speed analog-to-digital converter (ADC)-based wireline receivers, the Mueller–Muller clock and data recovery (MM-CDR) circuit has garnered increasing attention. But in the design stage, evaluating the loop performance of MM-CDR circuits in ADC-based wireline receivers is challenging due to the absence of a linearized model for a Mueller–Muller phase detector (MMPD). In this paper, a linearized model of the MMPD is proposed by analyzing the output probability of the MMPD in different transition patterns with random jitter injection, and the model is combined with an entire MM-CDR system to analyze the performance of the MM-CDR loop. Analysis of the linearized model and corresponding simulations indicate that when the reference voltage level in the MMPD is set equal to the amplitude of the average crossing voltage at the intersection of 011 and 110 patterns, the MMPD can obtain the maximum gain, which is determined by jitter, and the jitter transfer function and jitter tolerance can achieve optimum performance.

Noise-adapted recovery circuits for quantum error correction

Noise-adapted recovery circuits for quantum error correction

The Energy Circuit of the Exhaust Gas Heat Recovery Circuit of a 25 kW Diesel Generator

The purpose of the work is to describe the installation using differential equations and obtain approximate values before the experiment. In this paper, a constructive scheme of the experimental device is proposed, and the principle of its operation is described in detail. The power circuit of the device has been drawn up. Complex impedance, frequency function, amplitude-frequency characteristic and phase-frequency characteristic are obtained by mathematical transformation of the power circuit. The frequency response of the circuit is constructed. As a result of the calculations, we will obtain the amplitude frequency response and the phase frequency response. Using the found values of the characteristics, we will build graphs and draw conclusions about how the characteristics depend on the change in parameters and why the graph lines of the graphs are exactly the way they are.

A 16 Gb/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS

This paper presents a 16 Gb/s serial link transceiver implemented in 12-nm FinFET CMOS technology. The equalization scheme incorporates a 3-tap feed-forward equalizer (FFE) in the transmitter, a 5-stage continuous time linear equalizer (CTLE), and a 3-tap decision-feedback equalizer (DFE) in the receiver. The proposed FFE structure offers small step size and flexible configuration. The CTLE's high-frequency boost is augmented by integrating an active inductor. A high-accuracy clock and data recovery (CDR) circuit, featuring a cascaded two-step analog phase interpolator (PI) structure, is developed for data retiming. Occupying a footprint of 0.26 mm × 0.63 mm per lane, the transceiver test chip is packaged in a flip chip ball grid array (FC-BGA) module. Measurement results demonstrate a horizontal eye opening of 38 % at a bit error rate (BER) of 10−12 over a channel with 28 dB loss at 8 GHz. Moreover, the power consumption is 68.85 mW per lane at 16 Gb/s.

A strategy for quantum watermarking against geometric attacks

The development of new quantum watermarking is in full swing, and it is crucial to test the robustness of these proposed watermarking schemes. In this paper, different quantum circuits are introduced to realize geometric transformations on quantum images, which serve as a means of simulating geometric attacks on quantum watermark images. Receivers may get distorted images, and the extracted watermark images may also be disrupted. To recover the geometric order of the quantum watermark images, a strategy is proposed to identify the trajectory of qubit alterations. Quantum circuits can be designed accordingly to restore the original order of the watermark images, which receivers could use before the extraction process to mitigate the impact of geometric attacks. Experimental simulations demonstrate how attacks affect the quantum watermark images and the extracted watermark images. Additionally, it illustrates how quantum recovery circuits step by step act on images that have been geometrically attacked. An analysis of the complexity of geometric restoration circuits reveals that quantum circuits exhibit better performance compared to classical circuits.

A Self-Adaptive Dual-ILRO Clock-Recovery Technique for Two-Tone Battery-Free Crystal-Free Neural-Recording SoC.

Wireless implantable devices are widely used in medical treatment, which should meet clinical constraints such as longevity, miniaturization, and reliable communication. Wireless power transfer (WPT) can eliminate the battery to reduce system size and prolong device life, while it's challenging to generate a reliable clock without a crystal. In this work, we propose a self-adaptive dual-injection-locked-ring-oscillator (dual-ILRO) clock-recovery technique based on two-tone WPT and integrate it into a battery-free neural-recording SoC. The 2[Formula: see text]-order inter-modulation (IM2) component of the two WPT tones is extracted as a low-frequency reference for battery-free SoC, and the proposed self-adaptive dual-ILRO technique extends the lock range to ensure an anti-interference PVT-robust clock generation. The neural-recording SoC includes a low-noise signal acquisition unit, a power management unit, and a backscatter circuit to perform neural signal recording, wireless power harvesting, and neural data transmission. Benefiting from the 6.4 μW low power of the clock recovery circuit, the overall SoC power is cut down to 49.8 μW. In addition, the proposed clock-recovery technique enables both signal acquisition and uplink communication to perform as well as that synchronized by an ideal clock, i.e., an effective number of 9.6 bits and a bit error rate (BER) less than 4.8 × 10-7 in chip measurement. The SoC takes a die area of 2.05 mm 2, and an animal test is conducted in a Sprague-Dawley rat to validate the wireless neural-recording performance, compared to a crystal-synchronized commercial chip.

A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector

A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector

A 10-Gb/s Single-Loop Half-Rate DLL-Based Clock and Data Recovery Circuit for Forwarded-Clock Wireline Transceivers

A 10-Gb/s Single-Loop Half-Rate DLL-Based Clock and Data Recovery Circuit for Forwarded-Clock Wireline Transceivers

Detailed characterisation of precious metals and critical elements in anode slimes from the Olympic Dam copper refinery, South Australia

Together with silver (Ag) and gold (Au), which are almost always recovered, the impurity elements, arsenic (As), antimony (Sb), bismuth (Bi), tin (Sn), lead (Pb), selenium (Se) and tellurium (Te) are major components of anode slimes, a by-product of the electrorefining of impure copper. The Olympic Dam electrorefinery, South Australia, generates raw slimes (∼30 % Cu, 5–10 % Ag, 0.5–1 % Au, 3–4 % Bi, ∼2–3 % Sb, and 5–6 % As), which subsequently undergo decopperisation and then pH-neutralisation. Decopperisation involves treatment with steam and acid at 90 °C, giving a slime that contains ∼ 1 % Cu, 8–17 % Ag, ∼2% Au, ∼7% Bi, ∼4–5 % Sb, and ∼ 3 % As. pH-neutralisation is achieved by addition of NaOH and is the final step prior to cyanidation and precious metal recovery.Bulk chemical compositions, gross morphology and particle size distributions are complemented by high-magnification backscatter imaging and energy-dispersive X-ray analysis of individual particles in raw, decopperised, and pH-neutralised anode slimes. In a first micron-to-nanoscale approach, we use electron backscatter diffraction mapping to assess the crystallinity of individual component phases and a scanning transmission electron microscopy study on micron-sized slices extracted in-situ to confirm the crystal structure of a conspicuous BiAsO4 phase as rooseveltite. The results establish an in-depth understanding of element deportments in slimes and their evolution during sequential stages of treatment. Characterisation studies for Te, Se, Sb, Bi, and As are essential prerequisites for any design of metallurgical circuits for by-product recovery from anode slimes and/or electrolyte. This study aims to demonstrate that complementary cutting-edge microanalytical techniques widely used in mineralogy provide a level of detail essential when considering refinery slimes as a new source of critical commodities.

A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.

MATLAB/Simulink Modeling of Regenerative Recovery Circuit with Bidirectional DC-DC Converter for Scooter

Scooter, which is in the class of light electric vehicles, is a very common transportation vehicle, especially in big cities. Brushless direct current motor (BLDCM) is preferred in scooters. These motors are a type of electric motor used in light electric vehicles (LEV) due to their features such as high efficiency, long operating life, high speed and silence operation. Although the BLDCMs used in the propulsion system of the scooter have high efficiency, they do not have a long range due to their limited battery capacity. The biggest problem with scooters is their short range. In order to solve this negativity, manufacturers are working on different solutions. In this study, MATLAB/Simulink modelling of bidirectional DC-DC converter regenerative recovery circuit for scooter was carried out. It is aimed to increase the range with regenerative recovery. The system in the proposed study is implemented for a 300W BLDCM with a rated voltage of 24V. The effect of bidirectional DC-DC converter regenerative recovery is proven by MATLAB/Simulink results.

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique

This paper reports a reference-less frequency-detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 (Gb/s)/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> s and an energy efficiency of 1.3 pJ/bit.

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications.

The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE). Therefore, a 12T SRAM-hardened circuit (RHB-12T cell) for the soft error recovery is proposed using the radiation hardening design (RHBD) concept. To verify the performance of the RHB-12T, the proposed cell is simulated by the 28 nm CMOS process and compared with other hardened cells (Quatro-10T, WE-Quatro-12T, RHM-12T, RHD-12T, and RSP-14T). The simulation results show that the RHB-12T cell can recover not only from single-event upset caused by their sensitive nodes but also from single-event multi-node upset caused by their storage node pairs. The proposed cell exhibits 1.14×/1.23×/1.06× shorter read delay than Quatro-10T/WE-Quatro-12T/RSP-14T and 1.31×/1.11×/1.18×/1.37× shorter write delay than WE-Quatro-12T/RHM-12T/RHD-12T/RSP-14T. It also shows 1.35×/1.11×/1.04× higher read stability than Quatro-10T/RHM-12T/RHD-12T and 1.12×/1.04×/1.09× higher write ability than RHM-12T/RHD-12T/RSP-14T. All these improvements are achieved at the cost of a slightly larger area and power consumption.

Analysis of coherent-OFDM modulation for FSO communication over distribution with pointing errors

In this paper, we have analyzed a proposed coherent-orthogonal frequency division multiplexing (Co-OFDM) free space optical (FSO) communication system under ▪ distribution channel model. The proposed Co-OFDM FSO system contains a heterodyne mixer at the receiver section, which is used to convert the optical frequency to radio frequency (RF). After that, a carrier recovery circuit is used and then a synchronization circuit is used to correct the timing and phase of the received signal. Here, we derived an ABER expression and outage probability expression for the Co-OFDM FSO communication system under ▪ distribution channel model. We analyzed the results for different atmospheric turbulence (AT) conditions, pointing errors and the number of subcarriers. We have analyzed the system outage probability with varying received optical power and pointing error for different SNR thresholds and also analyzed for different AT conditions. In the results, we observed that the ABER performance improves as AT conditions improve, as the number of subcarriers decreases and as the pointing error decreases. Also, we observed that when AT conditions get worse, then to get same outage probability, we have to increase the SNR threshold. We have compared the Co-OFDM FSO system with popular modulation techniques PAM and PPM under ▪ distribution channel model.

New Clock Distribution System Based on Clock-Duty-Cycle-Modulation for Distributed Data-Aquisition System

This paper presents a clock distribution system based on a clock-centric modulation technique called clock-duty-cycle-modulation (CDCM) using the IOSERDESE2 primitives of Xilinx field programmable gate array (FPGA). The implemented CDCM techniques, CDCM-10-1.5 and CDCM-10-2.5, transfer 1-bit and 2-bit data per clock cycle by changing the trailing edge positions, respectively. This is the first work to succeed transmitting multi-bits per clock cycle by the CDCM. The developed system consists of the CDCM-based transceiver and the link layer protocol. All the components are implemented using the regular bunk functions in FPGA. The system is independent from a FPGA high-speed serial transceiver and does not require a clock data recovery circuit. In this work, two clock generators were utilized for clock recovery; one is a jitter cleaner IC, CDCE62002 from Texas Instruments, and the other is mixed-mode clock manager (MMCM) in FPGA. The 8-bit incremental data was transmitted by the CDCM modulated clock signal through an optical fiber. The jitters of the clock signals recovered by CDCE62002 were 5.8 and 6.8 ps in standard deviation for CDCM-10-1.5 and CDCM-10-2.5, respectively, when the reference clock frequency was 125 MHz. The averaged phase change of the recovered clock signal during the data transmission was smaller than 10 ps with respect to the clock phase recovered from the signal with the duty cycle of 50%. The obtained bit-error-rate (BER) was smaller than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

In this work, a high-speed four-channel 0.8-6Gb/s wireline receiver was reported. Based on spectrum-balancing (SB) equalizer and slicer amplitude attenuator, it can be automatically adjusted to the most suitable state, avoiding the underbalanced or over-balance caused by amplitude mismatch. Moreover, a first-order semi-digital dual-loop clock and data recovery circuit (SDDCDR) with a high-speed digital loop filter (DLF) is also integrated to simplify the structure and improve the tracking ability of frequency offset. The prototype was fabricated on a 130nm CMOS process with a core area of 0.38 mm2 for a single lane, consuming 97.3mW power at a 1.2V supply and tracking a 6966ppm frequency offset. In a 3m-cable test environment, the receiver sinusoidal jitter tolerance at high frequency is better than 0.22UI when 6Gb/s.

Analysis and Design Considerations of a Buck-Boost Energy Recovery-Based Power Converter for SRM Drive

This article presents the development of a dynamic model and a design approach for the recently proposed buck-boost energy recovery circuit (BBERC) based power converter for a switched reluctance motor (SRM). The advantage of an increased demagnetization voltage in reducing the commutation torque ripple is analyzed using analytical and simulation-based studies. Though there have been several studies on the steady state behavior of the energy recovery stage in the literature, the dynamics of the same have never been investigated. An equation-based small signal model to describe the dynamic behavior of the energy recovery stage is proposed, which can be used to estimate the overshoots and oscillations in the inductor current and capacitor voltage during the dynamics. This article also evaluates the effects of discontinuous conduction mode (DCM) of operation of the BBERC on the drive performance, which has also not been addressed in the prior art. Furthermore, a method for the design of the energy recovery stage considering the continuous conduction of the energy recovery inductor is proposed. Additionally, the advantages of BBERC are reemphasized by comparing it with other energy recovery-based topologies such as energy efficient C-dump converter (EECDC). The analyses presented in this article are validated with experiments and simulations.

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

SummaryThis paper reports a bang‐bang clock and data recovery circuit (BBCDR) with an ultra‐wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6‐to‐38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate‐current‐mismatch technique. Moreover, we accurately obtain an eight‐phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter‐based phase interpolator. A 65‐nm prototype of the developed BBCDR occupies an area of 0.07 mm2 and attains a bit error rate of less than 10−12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32‐Gb/s non‐return‐zero input, thus leading to 0.769‐pJ/bit energy efficiency.

A 0.2–7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers

For the measurement of high-speed communication signals, whether it is to check the signal’s bit error rate with a bit error rate tester or to record the signal’s eye diagram with an equivalent-time oscilloscope, a clock and data recovery (CDR) circuit is required to generate a trigger signal properly aligned to the input data signal. For the system under test where multiple communication protocols coexist, a wide operation frequency range and low jitter CDR circuit can undoubtedly improve the measurement efficiency and reduce the cost. However, obtaining broad frequency coverage and minimal recovery clock jitter simultaneously has always been a challenge in the design of CDR circuits. This paper proposes a CDR circuit combining a multi-band LC-VCO and a configurable frequency divider, which effectively expands the operating frequency range of the CDR while maintaining the low jitter of the recovered clock. A 0.2-7.1-Gb/s CDR circuits with a 1.9-ps RMS jitter of the recovered clock under a 7.1-Gb/s input PRBS signal is implemented in 65 nm CMOS. Compared with other LC-VCO based CDRs, the proposed CDR achieves better energy efficiency and lower jitter performance.

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.